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KVM: arm/arm64: vgic: Keep track of implementation revision 

As we are about to tweak implementation aspects of the VGIC emulation,
while still preserving some level of backwards compatibility support,
add a field to keep track of the implementation revision field which is
reported to the VM and to userspace.

Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Christoffer Dall 2018-07-16 15:06:19 +02:00 committed by Marc Zyngier
parent a2dca217da
commit aa075b0f30
4 changed files with 12 additions and 4 deletions
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3
include/kvm/arm_vgic.h
View File

@ -217,6 +217,9 @@ struct vgic_dist {
/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
u32 vgic_model; u32 vgic_model;
/* Implementation revision as reported in the GICD_IIDR */
u32 implementation_rev;
/* Do injected MSIs require an additional device ID? */ /* Do injected MSIs require an additional device ID? */
bool msis_require_devid; bool msis_require_devid;

1
virt/kvm/arm/vgic/vgic-init.c
View File

@ -298,6 +298,7 @@ int vgic_init(struct kvm *kvm)
vgic_debug_init(kvm); vgic_debug_init(kvm);
dist->implementation_rev = 0;
dist->initialized = true; dist->initialized = true;
out: out:

6
virt/kvm/arm/vgic/vgic-mmio-v2.c
View File

@ -25,19 +25,21 @@
static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu, static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
gpa_t addr, unsigned int len) gpa_t addr, unsigned int len)
{ {
struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
u32 value; u32 value;
switch (addr & 0x0c) { switch (addr & 0x0c) {
case GIC_DIST_CTRL: case GIC_DIST_CTRL:
value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0; value = vgic->enabled ? GICD_ENABLE : 0;
break; break;
case GIC_DIST_CTR: case GIC_DIST_CTR:
value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
value = (value >> 5) - 1; value = (value >> 5) - 1;
value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
break; break;
case GIC_DIST_IIDR: case GIC_DIST_IIDR:
value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
(IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
break; break;
default: default:

6
virt/kvm/arm/vgic/vgic-mmio-v3.c
View File

@ -62,16 +62,17 @@ bool vgic_supports_direct_msis(struct kvm *kvm)
static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
gpa_t addr, unsigned int len) gpa_t addr, unsigned int len)
{ {
struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
u32 value = 0; u32 value = 0;
switch (addr & 0x0c) { switch (addr & 0x0c) {
case GICD_CTLR: case GICD_CTLR:
if (vcpu->kvm->arch.vgic.enabled) if (vgic->enabled)
value |= GICD_CTLR_ENABLE_SS_G1; value |= GICD_CTLR_ENABLE_SS_G1;
value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
break; break;
case GICD_TYPER: case GICD_TYPER:
value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
value = (value >> 5) - 1; value = (value >> 5) - 1;
if (vgic_has_its(vcpu->kvm)) { if (vgic_has_its(vcpu->kvm)) {
value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
@ -82,6 +83,7 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
break; break;
case GICD_IIDR: case GICD_IIDR:
value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
(IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
break; break;
default: default: