[PATCH] dvb: frontend: s5h1420: fixes
Misc. fixes. Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net> Signed-off-by: Johannes Stezenbach <js@linuxtv.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Andrew de Quincey
Linus Torvalds
parent
cfbfce1566
commit
a9d6a80b41
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@ -48,7 +48,8 @@ struct s5h1420_state {
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};
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static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
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static int s5h1420_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings);
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static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
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struct dvb_frontend_tune_settings* fesettings);
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static int debug = 0;
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@ -91,7 +92,8 @@ static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
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switch(voltage) {
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case SEC_VOLTAGE_13:
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s5h1420_writereg(state, 0x3c, (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
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s5h1420_writereg(state, 0x3c,
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(s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
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break;
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case SEC_VOLTAGE_18:
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@ -112,18 +114,21 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
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switch(tone) {
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case SEC_TONE_ON:
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s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
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s5h1420_writereg(state, 0x3b,
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(s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
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break;
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case SEC_TONE_OFF:
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s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
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s5h1420_writereg(state, 0x3b,
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(s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
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break;
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}
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return 0;
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}
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static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
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static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
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struct dvb_diseqc_master_cmd* cmd)
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{
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struct s5h1420_state* state = fe->demodulator_priv;
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u8 val;
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@ -131,6 +136,9 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_m
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unsigned long timeout;
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int result = 0;
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if (cmd->msg_len > 8)
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return -EINVAL;
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/* setup for DISEQC */
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val = s5h1420_readreg(state, 0x3b);
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s5h1420_writereg(state, 0x3b, 0x02);
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@ -138,16 +146,17 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_m
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/* write the DISEQC command bytes */
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for(i=0; i< cmd->msg_len; i++) {
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s5h1420_writereg(state, 0x3c + i, cmd->msg[i]);
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s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
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}
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/* kick off transmission */
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s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | ((cmd->msg_len-1) << 4) | 0x08);
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s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
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((cmd->msg_len-1) << 4) | 0x08);
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/* wait for transmission to complete */
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timeout = jiffies + ((100*HZ) / 1000);
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while(time_before(jiffies, timeout)) {
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if (s5h1420_readreg(state, 0x3b) & 0x08)
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if (!(s5h1420_readreg(state, 0x3b) & 0x08))
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break;
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msleep(5);
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@ -161,7 +170,8 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_m
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return result;
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}
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static int s5h1420_recv_slave_reply (struct dvb_frontend* fe, struct dvb_diseqc_slave_reply* reply)
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static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
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struct dvb_diseqc_slave_reply* reply)
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{
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struct s5h1420_state* state = fe->demodulator_priv;
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u8 val;
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@ -205,7 +215,7 @@ static int s5h1420_recv_slave_reply (struct dvb_frontend* fe, struct dvb_diseqc_
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/* extract data */
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for(i=0; i< length; i++) {
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reply->msg[i] = s5h1420_readreg(state, 0x3c + i);
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reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
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}
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exit:
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@ -236,7 +246,7 @@ static int s5h1420_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minicm
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s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
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/* wait for transmission to complete */
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timeout = jiffies + ((20*HZ) / 1000);
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timeout = jiffies + ((100*HZ) / 1000);
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while(time_before(jiffies, timeout)) {
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if (!(s5h1420_readreg(state, 0x3b) & 0x08))
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break;
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@ -259,9 +269,9 @@ static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
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val = s5h1420_readreg(state, 0x14);
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if (val & 0x02)
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status |= FE_HAS_SIGNAL; // FIXME: not sure if this is right
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status |= FE_HAS_SIGNAL;
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if (val & 0x01)
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status |= FE_HAS_CARRIER; // FIXME: not sure if this is right
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status |= FE_HAS_CARRIER;
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val = s5h1420_readreg(state, 0x36);
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if (val & 0x01)
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status |= FE_HAS_VITERBI;
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@ -284,8 +294,8 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
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/* determine lock state */
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*status = s5h1420_get_status_bits(state);
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/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert the inversion,
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wait a bit and check again */
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/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
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the inversion, wait a bit and check again */
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if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
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val = s5h1420_readreg(state, 0x32);
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if ((val & 0x07) == 0x03) {
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@ -330,6 +340,10 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
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tmp = (tmp * 2 * 7) / 8;
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break;
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}
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if (tmp == 0) {
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printk("s5h1420: avoided division by 0\n");
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tmp = 1;
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}
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tmp = state->fclk / tmp;
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/* set the MPEG_CLK_INTL for the calculated data rate */
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@ -368,16 +382,21 @@ static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
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s5h1420_writereg(state, 0x46, 0x1d);
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mdelay(25);
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return (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
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*ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
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return 0;
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}
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static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
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{
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struct s5h1420_state* state = fe->demodulator_priv;
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u8 val = 0xff - s5h1420_readreg(state, 0x15);
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u8 val = s5h1420_readreg(state, 0x15);
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return (int) ((val << 8) | val);
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*strength = (u16) ((val << 8) | val);
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return 0;
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}
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static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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@ -386,7 +405,10 @@ static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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s5h1420_writereg(state, 0x46, 0x1f);
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mdelay(25);
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return (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
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*ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
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return 0;
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}
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static void s5h1420_reset(struct s5h1420_state* state)
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@ -396,11 +418,12 @@ static void s5h1420_reset(struct s5h1420_state* state)
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udelay(10);
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}
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static void s5h1420_setsymbolrate(struct s5h1420_state* state, struct dvb_frontend_parameters *p)
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static void s5h1420_setsymbolrate(struct s5h1420_state* state,
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struct dvb_frontend_parameters *p)
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{
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u64 val;
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val = (p->u.qpsk.symbol_rate / 1000) * (1<<24);
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val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
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if (p->u.qpsk.symbol_rate <= 21000000) {
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val *= 2;
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}
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@ -415,7 +438,7 @@ static void s5h1420_setsymbolrate(struct s5h1420_state* state, struct dvb_fronte
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static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
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{
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u64 val;
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u64 val = 0;
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int sampling = 2;
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if (s5h1420_readreg(state, 0x05) & 0x2)
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@ -427,10 +450,10 @@ static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
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val |= s5h1420_readreg(state, 0x13);
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s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
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val *= (state->fclk / 1000);
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val *= (state->fclk / 1000ULL);
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do_div(val, ((1<<24) * sampling));
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return (u32) (val * 1000);
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return (u32) (val * 1000ULL);
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}
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static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
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@ -463,46 +486,55 @@ static int s5h1420_getfreqoffset(struct s5h1420_state* state)
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/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
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* divide fclk by 1000000 to get the correct value. */
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val = - ((val * (state->fclk/1000000)) / (1<<24));
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val = (((-val) * (state->fclk/1000000)) / (1<<24));
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return val;
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}
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static void s5h1420_setfec(struct s5h1420_state* state, struct dvb_frontend_parameters *p)
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static void s5h1420_setfec_inversion(struct s5h1420_state* state,
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struct dvb_frontend_parameters *p)
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{
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u8 inversion = 0;
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if (p->inversion == INVERSION_OFF) {
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inversion = state->config->invert ? 0x08 : 0;
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} else if (p->inversion == INVERSION_ON) {
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inversion = state->config->invert ? 0 : 0x08;
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}
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if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
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s5h1420_writereg(state, 0x31, 0x00);
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s5h1420_writereg(state, 0x30, 0x3f);
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s5h1420_writereg(state, 0x31, 0x00 | inversion);
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} else {
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switch(p->u.qpsk.fec_inner) {
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case FEC_1_2:
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s5h1420_writereg(state, 0x31, 0x10);
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s5h1420_writereg(state, 0x30, 0x01);
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s5h1420_writereg(state, 0x31, 0x10 | inversion);
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break;
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case FEC_2_3:
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s5h1420_writereg(state, 0x31, 0x11);
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s5h1420_writereg(state, 0x30, 0x02);
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s5h1420_writereg(state, 0x31, 0x11 | inversion);
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break;
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case FEC_3_4:
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s5h1420_writereg(state, 0x31, 0x12);
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s5h1420_writereg(state, 0x30, 0x04);
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break;
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s5h1420_writereg(state, 0x31, 0x12 | inversion);
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break;
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case FEC_5_6:
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s5h1420_writereg(state, 0x31, 0x13);
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s5h1420_writereg(state, 0x30, 0x08);
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s5h1420_writereg(state, 0x31, 0x13 | inversion);
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break;
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case FEC_6_7:
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s5h1420_writereg(state, 0x31, 0x14);
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s5h1420_writereg(state, 0x30, 0x10);
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s5h1420_writereg(state, 0x31, 0x14 | inversion);
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break;
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case FEC_7_8:
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s5h1420_writereg(state, 0x31, 0x15);
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s5h1420_writereg(state, 0x30, 0x20);
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s5h1420_writereg(state, 0x31, 0x15 | inversion);
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break;
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default:
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@ -536,22 +568,6 @@ static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
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return FEC_NONE;
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}
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static void s5h1420_setinversion(struct s5h1420_state* state, struct dvb_frontend_parameters *p)
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{
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if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
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s5h1420_writereg(state, 0x31, 0x00);
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s5h1420_writereg(state, 0x30, 0x3f);
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} else {
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u8 tmp = s5h1420_readreg(state, 0x31) & 0xf7;
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tmp |= 0x10;
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if (p->inversion == INVERSION_ON)
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tmp |= 0x80;
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s5h1420_writereg(state, 0x31, tmp);
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}
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}
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static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
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{
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if (s5h1420_readreg(state, 0x32) & 0x08)
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@ -560,35 +576,35 @@ static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
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return INVERSION_OFF;
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}
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static int s5h1420_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
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static int s5h1420_set_frontend(struct dvb_frontend* fe,
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struct dvb_frontend_parameters *p)
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{
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struct s5h1420_state* state = fe->demodulator_priv;
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u32 frequency_delta;
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int frequency_delta;
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struct dvb_frontend_tune_settings fesettings;
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u32 tmp;
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/* check if we should do a fast-tune */
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memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
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s5h1420_get_tune_settings(fe, &fesettings);
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frequency_delta = p->frequency - state->tunedfreq;
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if ((frequency_delta > -fesettings.max_drift) && (frequency_delta < fesettings.max_drift) &&
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if ((frequency_delta > -fesettings.max_drift) &&
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(frequency_delta < fesettings.max_drift) &&
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(frequency_delta != 0) &&
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(state->fec_inner == p->u.qpsk.fec_inner) &&
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(state->symbol_rate == p->u.qpsk.symbol_rate)) {
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s5h1420_setfreqoffset(state, frequency_delta);
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if (state->config->pll_set) {
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s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
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state->config->pll_set(fe, p, &tmp);
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s5h1420_setfreqoffset(state, p->frequency - tmp);
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}
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return 0;
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}
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/* first of all, software reset */
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s5h1420_reset(state);
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/* set tuner PLL */
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if (state->config->pll_set) {
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s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
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state->config->pll_set(fe, p, &state->tunedfreq);
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s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
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}
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/* set s5h1420 fclk PLL according to desired symbol rate */
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if (p->u.qpsk.symbol_rate > 28000000) {
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state->fclk = 88000000;
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@ -609,8 +625,9 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
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/* set misc registers */
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s5h1420_writereg(state, 0x02, 0x00);
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s5h1420_writereg(state, 0x06, 0x00);
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s5h1420_writereg(state, 0x07, 0xb0);
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s5h1420_writereg(state, 0x0a, 0x67);
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s5h1420_writereg(state, 0x0a, 0xe7);
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s5h1420_writereg(state, 0x0b, 0x78);
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s5h1420_writereg(state, 0x0c, 0x48);
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s5h1420_writereg(state, 0x0d, 0x6b);
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@ -626,21 +643,26 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
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/* start QPSK */
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s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
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/* set the frequency offset to adjust for PLL inaccuracy */
|
||||
s5h1420_setfreqoffset(state, p->frequency - state->tunedfreq);
|
||||
/* set tuner PLL */
|
||||
if (state->config->pll_set) {
|
||||
s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
|
||||
state->config->pll_set(fe, p, &tmp);
|
||||
s5h1420_setfreqoffset(state, 0);
|
||||
}
|
||||
|
||||
/* set the reset of the parameters */
|
||||
s5h1420_setsymbolrate(state, p);
|
||||
s5h1420_setinversion(state, p);
|
||||
s5h1420_setfec(state, p);
|
||||
s5h1420_setfec_inversion(state, p);
|
||||
|
||||
state->fec_inner = p->u.qpsk.fec_inner;
|
||||
state->symbol_rate = p->u.qpsk.symbol_rate;
|
||||
state->postlocked = 0;
|
||||
state->tunedfreq = p->frequency;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s5h1420_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
|
||||
static int s5h1420_get_frontend(struct dvb_frontend* fe,
|
||||
struct dvb_frontend_parameters *p)
|
||||
{
|
||||
struct s5h1420_state* state = fe->demodulator_priv;
|
||||
|
||||
|
|
@ -652,7 +674,8 @@ static int s5h1420_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int s5h1420_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
|
||||
static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
|
||||
struct dvb_frontend_tune_settings* fesettings)
|
||||
{
|
||||
if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) {
|
||||
fesettings->min_delay_ms = 50;
|
||||
|
|
@ -717,7 +740,8 @@ static void s5h1420_release(struct dvb_frontend* fe)
|
|||
|
||||
static struct dvb_frontend_ops s5h1420_ops;
|
||||
|
||||
struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config, struct i2c_adapter* i2c)
|
||||
struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
|
||||
struct i2c_adapter* i2c)
|
||||
{
|
||||
struct s5h1420_state* state = NULL;
|
||||
u8 identity;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,9 @@ struct s5h1420_config
|
|||
/* the demodulator's i2c address */
|
||||
u8 demod_address;
|
||||
|
||||
/* does the inversion require inversion? */
|
||||
u8 invert:1;
|
||||
|
||||
/* PLL maintenance */
|
||||
int (*pll_init)(struct dvb_frontend* fe);
|
||||
int (*pll_set)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params, u32* freqout);
|
||||
|
|
|
|||
|
|
@ -480,6 +480,7 @@ static int s5h1420_pll_set(struct dvb_frontend* fe, struct dvb_frontend_paramete
|
|||
|
||||
static struct s5h1420_config s5h1420_config = {
|
||||
.demod_address = 0x53,
|
||||
.invert = 1,
|
||||
.pll_set = s5h1420_pll_set,
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue