drm/panel: Add display timing for Okaya RS800480T-7X0GP
Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver. The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz. This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/ Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel
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Required properties:
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- compatible: should be "okaya,rs800480t-7x0gp"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@ -973,6 +973,36 @@ static const struct panel_desc nec_nl4827hc19_05b = {
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.bus_format = MEDIA_BUS_FMT_RGB888_1X24
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};
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static const struct display_timing okaya_rs800480t_7x0gp_timing = {
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.pixelclock = { 30000000, 30000000, 40000000 },
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.hactive = { 800, 800, 800 },
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.hfront_porch = { 40, 40, 40 },
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.hback_porch = { 40, 40, 40 },
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.hsync_len = { 1, 48, 48 },
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.vactive = { 480, 480, 480 },
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.vfront_porch = { 13, 13, 13 },
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.vback_porch = { 29, 29, 29 },
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.vsync_len = { 3, 3, 3 },
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.flags = DISPLAY_FLAGS_DE_HIGH,
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};
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static const struct panel_desc okaya_rs800480t_7x0gp = {
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.timings = &okaya_rs800480t_7x0gp_timing,
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.num_timings = 1,
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.bpc = 6,
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.size = {
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.width = 154,
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.height = 87,
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},
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.delay = {
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.prepare = 41,
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.enable = 50,
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.unprepare = 41,
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.disable = 50,
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},
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.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
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};
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static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
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.clock = 25000,
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.hdisplay = 480,
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@ -1145,6 +1175,9 @@ static const struct of_device_id platform_of_match[] = {
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}, {
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.compatible = "nec,nl4827hc19-05b",
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.data = &nec_nl4827hc19_05b,
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}, {
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.compatible = "okaya,rs800480t-7x0gp",
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.data = &okaya_rs800480t_7x0gp,
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}, {
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.compatible = "ortustech,com43h4m85ulc",
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.data = &ortustech_com43h4m85ulc,
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