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Fixes for dtc warnings, fixes for ethernet transfers on rk3328, 

sd-card related fixes on both rk3328 ans rk3288-tinker and a
 regulator fix on rock64 and making ddc actually work on the
 Rock PI 4 due to missing the ddc bus.
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Merge tag 'v5.1-rockchip-dtfixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes

Fixes for dtc warnings, fixes for ethernet transfers on rk3328,
sd-card related fixes on both rk3328 ans rk3288-tinker and a
regulator fix on rock64 and making ddc actually work on the
Rock PI 4 due to missing the ddc bus.

* tag 'v5.1-rockchip-dtfixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Remove #address/#size-cells from rk3288-veyron gpio-keys
  ARM: dts: rockchip: Remove #address/#size-cells from rk3288 mipi_dsi
  ARM: dts: rockchip: Fix gpu opp node names for rk3288
  arm64: dts: rockchip: fix rk3328 sdmmc0 write errors
  arm64: dts: rockchip: fix rk3328 rgmii high tx error rate
  ARM: dts: rockchip: Fix SD card detection on rk3288-tinker
  arm64: dts: rockchip: Fix vcc_host1_5v GPIO polarity on rk3328-rock64
  ARM: dts: rockchip: fix rk3288 cpu opp node reference
  arm64: dts: rockchip: add DDC bus on Rock Pi 4
  arm64: dts: rockchip: fix rk3328-roc-cc gmac2io tx/rx_delay

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-07 15:15:31 -07:00
parent 3e372088ab 1a96665143
commit a97082852f
7 changed files with 44 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/rk3288-tinker.dtsi
View File

@ -254,6 +254,7 @@
};
vccio_sd: LDO_REG5 {
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
@ -430,7 +431,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
broken-cd;
disable-wp; /* wp not hooked up */
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;

2
arch/arm/boot/dts/rk3288-veyron.dtsi
View File

@ -25,8 +25,6 @@
gpio_keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_l>;

20
arch/arm/boot/dts/rk3288.dtsi
View File

@ -70,7 +70,7 @@
compatible = "arm,cortex-a12";
reg = <0x501>;
resets = <&cru SRST_CORE1>;
operating-points = <&cpu_opp_table>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@ -80,7 +80,7 @@
compatible = "arm,cortex-a12";
reg = <0x502>;
resets = <&cru SRST_CORE2>;
operating-points = <&cpu_opp_table>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@ -90,7 +90,7 @@
compatible = "arm,cortex-a12";
reg = <0x503>;
resets = <&cru SRST_CORE3>;
operating-points = <&cpu_opp_table>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@ -1119,8 +1119,6 @@
clock-names = "ref", "pclk";
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
@ -1282,27 +1280,27 @@
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
opp@100000000 {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <950000>;
};
opp@200000000 {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <950000>;
};
opp@300000000 {
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
};
opp@400000000 {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
opp@500000000 {
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1200000>;
};
opp@600000000 {
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1250000>;
};

4
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
View File

@ -108,8 +108,8 @@
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x25>;
rx_delay = <0x11>;
tx_delay = <0x24>;
rx_delay = <0x18>;
status = "okay";
};

3
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
View File

@ -46,8 +46,7 @@
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";

58
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -1445,11 +1445,11 @@
sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
};
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
};
sdmmc0_dectn: sdmmc0-dectn {
@ -1461,14 +1461,14 @@
};
sdmmc0_bus1: sdmmc0-bus1 {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
};
sdmmc0_bus4: sdmmc0-bus4 {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
<1 RK_PA1 1 &pcfg_pull_up_4ma>,
<1 RK_PA2 1 &pcfg_pull_up_4ma>,
<1 RK_PA3 1 &pcfg_pull_up_4ma>;
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
<1 RK_PA1 1 &pcfg_pull_up_8ma>,
<1 RK_PA2 1 &pcfg_pull_up_8ma>,
<1 RK_PA3 1 &pcfg_pull_up_8ma>;
};
sdmmc0_gpio: sdmmc0-gpio {
@ -1642,50 +1642,50 @@
rgmiim1_pins: rgmiim1-pins {
rockchip,pins =
/* mac_txclk */
<1 RK_PB4 2 &pcfg_pull_none_12ma>,
<1 RK_PB4 2 &pcfg_pull_none_8ma>,
/* mac_rxclk */
<1 RK_PB5 2 &pcfg_pull_none_2ma>,
<1 RK_PB5 2 &pcfg_pull_none_4ma>,
/* mac_mdio */
<1 RK_PC3 2 &pcfg_pull_none_2ma>,
<1 RK_PC3 2 &pcfg_pull_none_4ma>,
/* mac_txen */
<1 RK_PD1 2 &pcfg_pull_none_12ma>,
<1 RK_PD1 2 &pcfg_pull_none_8ma>,
/* mac_clk */
<1 RK_PC5 2 &pcfg_pull_none_2ma>,
<1 RK_PC5 2 &pcfg_pull_none_4ma>,
/* mac_rxdv */
<1 RK_PC6 2 &pcfg_pull_none_2ma>,
<1 RK_PC6 2 &pcfg_pull_none_4ma>,
/* mac_mdc */
<1 RK_PC7 2 &pcfg_pull_none_2ma>,
<1 RK_PC7 2 &pcfg_pull_none_4ma>,
/* mac_rxd1 */
<1 RK_PB2 2 &pcfg_pull_none_2ma>,
<1 RK_PB2 2 &pcfg_pull_none_4ma>,
/* mac_rxd0 */
<1 RK_PB3 2 &pcfg_pull_none_2ma>,
<1 RK_PB3 2 &pcfg_pull_none_4ma>,
/* mac_txd1 */
<1 RK_PB0 2 &pcfg_pull_none_12ma>,
<1 RK_PB0 2 &pcfg_pull_none_8ma>,
/* mac_txd0 */
<1 RK_PB1 2 &pcfg_pull_none_12ma>,
<1 RK_PB1 2 &pcfg_pull_none_8ma>,
/* mac_rxd3 */
<1 RK_PB6 2 &pcfg_pull_none_2ma>,
<1 RK_PB6 2 &pcfg_pull_none_4ma>,
/* mac_rxd2 */
<1 RK_PB7 2 &pcfg_pull_none_2ma>,
<1 RK_PB7 2 &pcfg_pull_none_4ma>,
/* mac_txd3 */
<1 RK_PC0 2 &pcfg_pull_none_12ma>,
<1 RK_PC0 2 &pcfg_pull_none_8ma>,
/* mac_txd2 */
<1 RK_PC1 2 &pcfg_pull_none_12ma>,
<1 RK_PC1 2 &pcfg_pull_none_8ma>,
/* mac_txclk */
<0 RK_PB0 1 &pcfg_pull_none>,
<0 RK_PB0 1 &pcfg_pull_none_8ma>,
/* mac_txen */
<0 RK_PB4 1 &pcfg_pull_none>,
<0 RK_PB4 1 &pcfg_pull_none_8ma>,
/* mac_clk */
<0 RK_PD0 1 &pcfg_pull_none>,
<0 RK_PD0 1 &pcfg_pull_none_4ma>,
/* mac_txd1 */
<0 RK_PC0 1 &pcfg_pull_none>,
<0 RK_PC0 1 &pcfg_pull_none_8ma>,
/* mac_txd0 */
<0 RK_PC1 1 &pcfg_pull_none>,
<0 RK_PC1 1 &pcfg_pull_none_8ma>,
/* mac_txd3 */
<0 RK_PC7 1 &pcfg_pull_none>,
<0 RK_PC7 1 &pcfg_pull_none_8ma>,
/* mac_txd2 */
<0 RK_PC6 1 &pcfg_pull_none>;
<0 RK_PC6 1 &pcfg_pull_none_8ma>;
};
rmiim1_pins: rmiim1-pins {

1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
View File

@ -158,6 +158,7 @@
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";