ASoC: topology: Fix bclk and fsync inversion in set_link_hw_format()
The values of bclk and fsync are inverted WRT the codec. But the existing solution already works for Broadwell, see the alsa-lib config: `alsa-lib/src/conf/topology/broadwell/broadwell.conf` This commit provides the backwards-compatible solution to fix this misuse. Signed-off-by: Kirill Marinushkin <k.marinushkin@gmail.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Tested-by: Pan Xiuli <xiuli.pan@linux.intel.com> Tested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.de> Cc: Mark Brown <broonie@kernel.org> Cc: Liam Girdwood <liam.r.girdwood@linux.intel.com> Cc: linux-kernel@vger.kernel.org Cc: alsa-devel@alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -160,6 +160,18 @@
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#define SND_SOC_TPLG_LNK_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2)
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#define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3)
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/* DAI topology BCLK parameter
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* For the backwards capability, by default codec is bclk master
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*/
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#define SND_SOC_TPLG_BCLK_CM 0 /* codec is bclk master */
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#define SND_SOC_TPLG_BCLK_CS 1 /* codec is bclk slave */
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/* DAI topology FSYNC parameter
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* For the backwards capability, by default codec is fsync master
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*/
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#define SND_SOC_TPLG_FSYNC_CM 0 /* codec is fsync master */
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#define SND_SOC_TPLG_FSYNC_CS 1 /* codec is fsync slave */
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/*
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* Block Header.
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* This header precedes all object and object arrays below.
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@ -315,8 +327,8 @@ struct snd_soc_tplg_hw_config {
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__u8 clock_gated; /* 1 if clock can be gated to save power */
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__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
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__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
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__u8 bclk_master; /* 1 for master of BCLK, 0 for slave */
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__u8 fsync_master; /* 1 for master of FSYNC, 0 for slave */
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__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
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__u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
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__u8 mclk_direction; /* 0 for input, 1 for output */
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__le16 reserved; /* for 32bit alignment */
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__le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */
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@ -2019,13 +2019,15 @@ static void set_link_hw_format(struct snd_soc_dai_link *link,
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link->dai_fmt |= SND_SOC_DAIFMT_IB_IF;
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/* clock masters */
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bclk_master = hw_config->bclk_master;
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fsync_master = hw_config->fsync_master;
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if (!bclk_master && !fsync_master)
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bclk_master = (hw_config->bclk_master ==
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SND_SOC_TPLG_BCLK_CM);
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fsync_master = (hw_config->fsync_master ==
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SND_SOC_TPLG_FSYNC_CM);
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if (bclk_master && fsync_master)
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link->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
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else if (bclk_master && !fsync_master)
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link->dai_fmt |= SND_SOC_DAIFMT_CBS_CFM;
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else if (!bclk_master && fsync_master)
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link->dai_fmt |= SND_SOC_DAIFMT_CBS_CFM;
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else if (bclk_master && !fsync_master)
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link->dai_fmt |= SND_SOC_DAIFMT_CBM_CFS;
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else
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link->dai_fmt |= SND_SOC_DAIFMT_CBS_CFS;
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