avr32: Add MMIO address definitions for certain controllers
Hardcoded MMIO base addresses are used a few places throughout the platform code. Move these into the chip-specific header file so that adding support for new chips becomes a bit easier. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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@ -16,6 +16,8 @@
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#include <linux/device.h>
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#include <linux/string.h>
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#include <mach/chip.h>
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#include "clock.h"
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static DEFINE_SPINLOCK(clk_lock);
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@ -46,4 +46,12 @@
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#define DMAC_DMAREQ_2 9
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#define DMAC_DMAREQ_3 10
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/*
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* Base addresses of controllers that may be accessed early by
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* platform code.
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*/
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#define PM_BASE 0xfff00000
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#define HMATRIX_BASE 0xfff00800
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#define SDRAMC_BASE 0xfff03800
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#endif /* __ASM_ARCH_AT32AP700X_H__ */
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@ -14,12 +14,10 @@
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#include <asm/cacheflush.h>
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#include <asm/sysreg.h>
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#include <mach/chip.h>
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#include <mach/pm.h>
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#include <mach/sram.h>
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/* FIXME: This is only valid for AP7000 */
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#define SDRAMC_BASE 0xfff03800
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#include "sdramc.h"
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#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
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@ -4,14 +4,6 @@
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#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
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#define __ARCH_AVR32_MACH_AT32AP_PM_H__
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/*
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* We can reduce the code size a bit by using a constant here. Since
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* this file is only used on AVR32 AP CPUs with segmentation enabled,
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* it's safe to not use ioremap. Generic drivers should of course
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* never do this.
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*/
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#define AT32_PM_BASE 0xfff00000
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/* PM register offsets */
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#define PM_MCCTRL 0x0000
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#define PM_CKSEL 0x0004
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@ -113,8 +105,8 @@
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/* Register access macros */
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#define pm_readl(reg) \
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__raw_readl((void __iomem __force *)AT32_PM_BASE + PM_##reg)
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__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
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#define pm_writel(reg,value) \
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__raw_writel((value), (void __iomem __force *)AT32_PM_BASE + PM_##reg)
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__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
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#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
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