ARM: OMAP4+/AM33xx: CM: add common API for cm_wait_module_idle
Adds a generic CM driver API for waiting module to enter idle / standby. The SoC specific implementations are registered through cm_ll_data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -45,18 +45,23 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
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* struct cm_ll_data - fn ptrs to per-SoC CM function implementations
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* struct cm_ll_data - fn ptrs to per-SoC CM function implementations
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* @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
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* @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
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* @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
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* @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
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* @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
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*/
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*/
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struct cm_ll_data {
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struct cm_ll_data {
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int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
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int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
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u8 *idlest_reg_id);
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u8 *idlest_reg_id);
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int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
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int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
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u8 idlest_shift);
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u8 idlest_shift);
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int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
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u8 idlest_shift);
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};
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};
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extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
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extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
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u8 *idlest_reg_id);
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u8 *idlest_reg_id);
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int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
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int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
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u8 idlest_shift);
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u8 idlest_shift);
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int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
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u8 idlest_shift);
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extern int cm_register(struct cm_ll_data *cld);
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extern int cm_register(struct cm_ll_data *cld);
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extern int cm_unregister(struct cm_ll_data *cld);
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extern int cm_unregister(struct cm_ll_data *cld);
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@ -250,14 +250,17 @@ static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
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/**
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/**
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* am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
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* am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
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* state
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* state
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* @part: CM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @bit_shift: bit shift for the register, ignored for AM33xx
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*
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*
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* Wait for the module IDLEST to be disabled. Some PRCM transition,
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* Wait for the module IDLEST to be disabled. Some PRCM transition,
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* like reset assertion or parent clock de-activation must wait the
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* like reset assertion or parent clock de-activation must wait the
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* module to be fully disabled.
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* module to be fully disabled.
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*/
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*/
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int am33xx_cm_wait_module_idle(u16 inst, u16 clkctrl_offs)
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static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
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u8 bit_shift)
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{
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{
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int i = 0;
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int i = 0;
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@ -364,6 +367,7 @@ struct clkdm_ops am33xx_clkdm_operations = {
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static struct cm_ll_data am33xx_cm_ll_data = {
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static struct cm_ll_data am33xx_cm_ll_data = {
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.wait_module_ready = &am33xx_cm_wait_module_ready,
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.wait_module_ready = &am33xx_cm_wait_module_ready,
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.wait_module_idle = &am33xx_cm_wait_module_idle,
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};
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};
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int __init am33xx_cm_init(void)
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int __init am33xx_cm_init(void)
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@ -382,16 +382,11 @@ void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
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int am33xx_cm_init(void);
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int am33xx_cm_init(void);
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#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
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#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
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int am33xx_cm_wait_module_idle(u16 inst, u16 clkctrl_offs);
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extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
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extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
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u16 clkctrl_offs);
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u16 clkctrl_offs);
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extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
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extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
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u16 clkctrl_offs);
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u16 clkctrl_offs);
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#else
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#else
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static inline int am33xx_cm_wait_module_idle(u16 inst, u16 clkctrl_offs)
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{
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return 0;
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}
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static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
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static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
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u16 clkctrl_offs)
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u16 clkctrl_offs)
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{
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{
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@ -97,6 +97,32 @@ int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
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idlest_shift);
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idlest_shift);
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}
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}
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/**
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* omap_cm_wait_module_idle - wait for a module to enter idle or standby
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* @part: PRCM partition
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* @prcm_mod: PRCM module offset
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* @idlest_reg: CM_IDLESTx register
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* @idlest_shift: shift of the bit in the CM_IDLEST* register to check
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*
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* Wait for the PRCM to indicate that the module identified by
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* (@prcm_mod, @idlest_id, @idlest_shift) is no longer clocked. Return
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* 0 upon success, -EBUSY if the module doesn't enable in time, or
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* -EINVAL if no per-SoC wait_module_idle() function pointer has been
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* registered or if the idlest register is unknown on the SoC.
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*/
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int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
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u8 idlest_shift)
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{
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if (!cm_ll_data->wait_module_idle) {
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WARN_ONCE(1, "cm: %s: no low-level function defined\n",
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__func__);
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return -EINVAL;
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}
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return cm_ll_data->wait_module_idle(part, prcm_mod, idlest_reg,
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idlest_shift);
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}
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/**
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/**
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* cm_register - register per-SoC low-level data with the CM
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* cm_register - register per-SoC low-level data with the CM
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* @cld: low-level per-SoC OMAP CM data & function pointers to register
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* @cld: low-level per-SoC OMAP CM data & function pointers to register
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@ -293,12 +293,14 @@ static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @bit_shift: Bit shift for the register, ignored for OMAP4+
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*
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*
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* Wait for the module IDLEST to be disabled. Some PRCM transition,
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* Wait for the module IDLEST to be disabled. Some PRCM transition,
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* like reset assertion or parent clock de-activation must wait the
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* like reset assertion or parent clock de-activation must wait the
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* module to be fully disabled.
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* module to be fully disabled.
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*/
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*/
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int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 clkctrl_offs)
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static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
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u8 bit_shift)
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{
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{
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int i = 0;
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int i = 0;
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@ -510,6 +512,7 @@ struct clkdm_ops am43xx_clkdm_operations = {
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static struct cm_ll_data omap4xxx_cm_ll_data = {
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static struct cm_ll_data omap4xxx_cm_ll_data = {
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.wait_module_ready = &omap4_cminst_wait_module_ready,
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.wait_module_ready = &omap4_cminst_wait_module_ready,
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.wait_module_idle = &omap4_cminst_wait_module_idle,
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};
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};
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int __init omap4_cm_init(void)
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int __init omap4_cm_init(void)
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@ -16,7 +16,6 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
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void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
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void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
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void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
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void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
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void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
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void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
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int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 clkctrl_offs);
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extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
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extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
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u16 clkctrl_offs);
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u16 clkctrl_offs);
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extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
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extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
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@ -1026,9 +1026,9 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
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if (oh->flags & HWMOD_NO_IDLEST)
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if (oh->flags & HWMOD_NO_IDLEST)
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return 0;
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return 0;
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return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
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return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
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oh->clkdm->cm_inst,
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oh->clkdm->cm_inst,
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oh->prcm.omap4.clkctrl_offs);
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oh->prcm.omap4.clkctrl_offs, 0);
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}
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}
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/**
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/**
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@ -1051,8 +1051,8 @@ static int _am33xx_wait_target_disable(struct omap_hwmod *oh)
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if (oh->flags & HWMOD_NO_IDLEST)
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if (oh->flags & HWMOD_NO_IDLEST)
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return 0;
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return 0;
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return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst,
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return omap_cm_wait_module_idle(0, oh->clkdm->cm_inst,
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oh->prcm.omap4.clkctrl_offs);
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oh->prcm.omap4.clkctrl_offs, 0);
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}
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}
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/**
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/**
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