sound fixes for 4.4-rc7
This shouldn't be a nightmare before Christmas: just a handful small device-specific fixes for various ASoC and HD-audio drivers. Most of them are stable fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJWeq2LAAoJEGwxgFQ9KSmkxpsQAIhERdXPVKSM6WhBA45lsblD 2dqfxGCpCw0ta0GEWuvZODxDk3N21LQ+OMH4NWnS//qYATIaQMAq1d1/gGF7IibZ 8HpHxtbHknGrzcdDhG1M2hWLQbl2psyz8CvPJ8GuGt9BSEEMLu2oCxdovvqMEanz WFW06622XO52+giH+lelqBtS/yIypUuovEx96wiwKUX0pKqzPBlS1+fBjIxiQGx6 aEuD1wdjRwlP+P7UjrrpaNy+b7BVlodVRrOVFQzs+MouAhpoyumzD1IM4bmL65ra 1M3WYbsgYmoCTpsQGBl2BAarc1AJRaJvDoRSd+b/7gqroLjrUIldLMlqm3AQSlP8 a7+VSsIgtmrvYv2GM8B0N17av2+vY2TdE/Uf9znlz0SyMm6fiKqfjSUQWUq5sqFr fGYdZWv513afeiQIYA31FPX3wQKd32EQzfeP/No+hjwitzZ15q+NHylZnSySL13G Rm824cCAKrte8OZjgSIxOrFDpZj2/6Qk8kmT+dOnjIGBxn/k8ALKt7UY48TBMzKI jvHIFEPXitIx5RZhjvWNa3mn0mveWZ69YXJsAXxZGL6W4/bBoEh/MbXgMKwwvaTo nbDssWg/w1TfsgWxC3nFb0iso/8L1kH7bU9397kJ5vtIygj8fdSUZr4FyqZFKAN4 XuQ/WlEk1vj8GIfbFWdG =z4qE -----END PGP SIGNATURE----- Merge tag 'sound-4.4-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "This shouldn't be a nightmare before Christmas: just a handful small device-specific fixes for various ASoC and HD-audio drivers. Most of them are stable fixes" * tag 'sound-4.4-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: ALSA: hda/realtek - Fix silent headphone output on MacPro 4,1 (v2) ASoC: fsl_sai: fix no frame clk in master mode ALSA: hda - Set SKL+ hda controller power at freeze() and thaw() ASoC: sgtl5000: fix VAG power up timing ASoC: rockchip: spdif: Set transmit data level to 16 samples ASoC: wm8974: set cache type for regmap ASoC: es8328: Fix shifts for mixer switches ASoC: davinci-mcasp: Fix XDATA check in mcasp_start_tx ASoC: es8328: Fix deemphasis values
This commit is contained in:
commit
a88164345b
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@ -954,6 +954,36 @@ static int azx_resume(struct device *dev)
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}
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}
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#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
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#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
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#ifdef CONFIG_PM_SLEEP
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/* put codec down to D3 at hibernation for Intel SKL+;
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* otherwise BIOS may still access the codec and screw up the driver
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*/
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#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
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#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
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#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
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#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
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static int azx_freeze_noirq(struct device *dev)
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{
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struct pci_dev *pci = to_pci_dev(dev);
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if (IS_SKL_PLUS(pci))
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pci_set_power_state(pci, PCI_D3hot);
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return 0;
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}
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static int azx_thaw_noirq(struct device *dev)
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{
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struct pci_dev *pci = to_pci_dev(dev);
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if (IS_SKL_PLUS(pci))
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pci_set_power_state(pci, PCI_D0);
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM
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static int azx_runtime_suspend(struct device *dev)
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static int azx_runtime_suspend(struct device *dev)
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{
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{
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@ -1063,6 +1093,10 @@ static int azx_runtime_idle(struct device *dev)
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static const struct dev_pm_ops azx_pm = {
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static const struct dev_pm_ops azx_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
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SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
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#ifdef CONFIG_PM_SLEEP
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.freeze_noirq = azx_freeze_noirq,
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.thaw_noirq = azx_thaw_noirq,
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#endif
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SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
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SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
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};
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};
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@ -1775,6 +1775,7 @@ enum {
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ALC889_FIXUP_MBA11_VREF,
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ALC889_FIXUP_MBA11_VREF,
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ALC889_FIXUP_MBA21_VREF,
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ALC889_FIXUP_MBA21_VREF,
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ALC889_FIXUP_MP11_VREF,
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ALC889_FIXUP_MP11_VREF,
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ALC889_FIXUP_MP41_VREF,
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ALC882_FIXUP_INV_DMIC,
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ALC882_FIXUP_INV_DMIC,
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ALC882_FIXUP_NO_PRIMARY_HP,
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ALC882_FIXUP_NO_PRIMARY_HP,
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ALC887_FIXUP_ASUS_BASS,
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ALC887_FIXUP_ASUS_BASS,
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@ -1863,7 +1864,7 @@ static void alc889_fixup_mbp_vref(struct hda_codec *codec,
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const struct hda_fixup *fix, int action)
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const struct hda_fixup *fix, int action)
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{
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{
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struct alc_spec *spec = codec->spec;
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struct alc_spec *spec = codec->spec;
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static hda_nid_t nids[2] = { 0x14, 0x15 };
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static hda_nid_t nids[3] = { 0x14, 0x15, 0x19 };
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int i;
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int i;
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if (action != HDA_FIXUP_ACT_INIT)
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if (action != HDA_FIXUP_ACT_INIT)
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@ -2153,6 +2154,12 @@ static const struct hda_fixup alc882_fixups[] = {
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.chained = true,
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.chained = true,
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.chain_id = ALC885_FIXUP_MACPRO_GPIO,
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.chain_id = ALC885_FIXUP_MACPRO_GPIO,
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},
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},
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[ALC889_FIXUP_MP41_VREF] = {
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.type = HDA_FIXUP_FUNC,
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.v.func = alc889_fixup_mbp_vref,
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.chained = true,
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.chain_id = ALC885_FIXUP_MACPRO_GPIO,
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},
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[ALC882_FIXUP_INV_DMIC] = {
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[ALC882_FIXUP_INV_DMIC] = {
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.type = HDA_FIXUP_FUNC,
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.type = HDA_FIXUP_FUNC,
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.v.func = alc_fixup_inv_dmic,
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.v.func = alc_fixup_inv_dmic,
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@ -2235,7 +2242,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = {
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SND_PCI_QUIRK(0x106b, 0x3f00, "Macbook 5,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x3f00, "Macbook 5,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4000, "MacbookPro 5,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4000, "MacbookPro 5,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4100, "Macmini 3,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4100, "Macmini 3,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4200, "Mac Pro 5,1", ALC885_FIXUP_MACPRO_GPIO),
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SND_PCI_QUIRK(0x106b, 0x4200, "Mac Pro 4,1/5,1", ALC889_FIXUP_MP41_VREF),
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SND_PCI_QUIRK(0x106b, 0x4300, "iMac 9,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4300, "iMac 9,1", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4600, "MacbookPro 5,2", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4600, "MacbookPro 5,2", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4900, "iMac 9,1 Aluminum", ALC889_FIXUP_IMAC91_VREF),
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SND_PCI_QUIRK(0x106b, 0x4900, "iMac 9,1 Aluminum", ALC889_FIXUP_IMAC91_VREF),
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@ -85,7 +85,15 @@ static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
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static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
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static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
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static const struct {
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int rate;
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unsigned int val;
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} deemph_settings[] = {
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{ 0, ES8328_DACCONTROL6_DEEMPH_OFF },
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{ 32000, ES8328_DACCONTROL6_DEEMPH_32k },
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{ 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
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{ 48000, ES8328_DACCONTROL6_DEEMPH_48k },
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};
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static int es8328_set_deemph(struct snd_soc_codec *codec)
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static int es8328_set_deemph(struct snd_soc_codec *codec)
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{
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{
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@ -97,21 +105,22 @@ static int es8328_set_deemph(struct snd_soc_codec *codec)
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* rate.
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* rate.
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*/
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*/
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if (es8328->deemph) {
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if (es8328->deemph) {
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best = 1;
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best = 0;
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for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
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for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
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if (abs(deemph_settings[i] - es8328->playback_fs) <
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if (abs(deemph_settings[i].rate - es8328->playback_fs) <
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abs(deemph_settings[best] - es8328->playback_fs))
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abs(deemph_settings[best].rate - es8328->playback_fs))
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best = i;
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best = i;
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}
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}
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val = best << 1;
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val = deemph_settings[best].val;
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} else {
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} else {
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val = 0;
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val = ES8328_DACCONTROL6_DEEMPH_OFF;
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}
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}
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dev_dbg(codec->dev, "Set deemphasis %d\n", val);
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dev_dbg(codec->dev, "Set deemphasis %d\n", val);
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return snd_soc_update_bits(codec, ES8328_DACCONTROL6, 0x6, val);
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return snd_soc_update_bits(codec, ES8328_DACCONTROL6,
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ES8328_DACCONTROL6_DEEMPH_MASK, val);
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}
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}
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static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
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static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
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@ -153,6 +153,7 @@ int es8328_probe(struct device *dev, struct regmap *regmap);
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#define ES8328_DACCONTROL6_CLICKFREE (1 << 3)
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#define ES8328_DACCONTROL6_CLICKFREE (1 << 3)
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#define ES8328_DACCONTROL6_DAC_INVR (1 << 4)
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#define ES8328_DACCONTROL6_DAC_INVR (1 << 4)
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#define ES8328_DACCONTROL6_DAC_INVL (1 << 5)
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#define ES8328_DACCONTROL6_DAC_INVL (1 << 5)
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#define ES8328_DACCONTROL6_DEEMPH_MASK (3 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6)
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@ -189,6 +189,7 @@ static int power_vag_event(struct snd_soc_dapm_widget *w,
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
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snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
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SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
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SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
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msleep(400);
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break;
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break;
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case SND_SOC_DAPM_PRE_PMD:
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case SND_SOC_DAPM_PRE_PMD:
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@ -574,6 +574,7 @@ static const struct regmap_config wm8974_regmap = {
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.max_register = WM8974_MONOMIX,
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.max_register = WM8974_MONOMIX,
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.reg_defaults = wm8974_reg_defaults,
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.reg_defaults = wm8974_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
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.num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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};
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static int wm8974_probe(struct snd_soc_codec *codec)
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static int wm8974_probe(struct snd_soc_codec *codec)
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@ -223,8 +223,8 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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/* wait for XDATA to be cleared */
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/* wait for XDATA to be cleared */
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cnt = 0;
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cnt = 0;
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while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
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while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
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~XRDATA) && (cnt < 100000))
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(cnt < 100000))
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cnt++;
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cnt++;
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/* Release TX state machine */
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/* Release TX state machine */
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@ -505,6 +505,24 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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/*
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* For sai master mode, after several open/close sai,
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* there will be no frame clock, and can't recover
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* anymore. Add software reset to fix this issue.
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* This is a hardware bug, and will be fix in the
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* next sai version.
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*/
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if (!sai->is_slave_mode) {
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/* Software Reset for both Tx and Rx */
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regmap_write(sai->regmap,
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FSL_SAI_TCSR, FSL_SAI_CSR_SR);
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regmap_write(sai->regmap,
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FSL_SAI_RCSR, FSL_SAI_CSR_SR);
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/* Clear SR bit to finish the reset */
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regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
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regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
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}
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}
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}
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break;
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break;
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default:
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default:
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@ -152,8 +152,10 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
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SPDIF_DMACR_TDE_ENABLE,
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SPDIF_DMACR_TDE_ENABLE |
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SPDIF_DMACR_TDE_ENABLE);
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SPDIF_DMACR_TDL_MASK,
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SPDIF_DMACR_TDE_ENABLE |
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SPDIF_DMACR_TDL(16));
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if (ret != 0)
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if (ret != 0)
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return ret;
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return ret;
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@ -42,7 +42,7 @@
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#define SPDIF_DMACR_TDL_SHIFT 0
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#define SPDIF_DMACR_TDL_SHIFT 0
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#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL_MASK (0x1f << SDPIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
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|
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/*
|
/*
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* XFER
|
* XFER
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||||||
|
|
Loading…
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