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Merge branch 'for-4.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata 

Pull libata fixes from Tejun Heo:
 "Nothing too interesting. David Milburn improved a corner case
  misbehavior during hotplug. Other than that, minor driver-specific
  fixes"

* 'for-4.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
  libata: sata_down_spd_limit should return if driver has not recorded sstatus speed
  ahci: mtk: Change driver name to ahci-mtk
  ahci: qoriq: refine port register configuration
  pata_pdc2027x : make pdc2027x_*_timing structures const
  pata_pdc2027x: Remove unnecessary error check
  ata: mediatek: Fix typo in module description
This commit is contained in:
Linus Torvalds 2017-12-11 17:05:33 -08:00
parent bfb529ee79 2dc0b46b5e
commit a83cb7e6ad
4 changed files with 30 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/ata/ahci_mtk.c
View File

@ -1,5 +1,5 @@
/* /*
* MeidaTek AHCI SATA driver * MediaTek AHCI SATA driver
* *
* Copyright (c) 2017 MediaTek Inc. * Copyright (c) 2017 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com> * Author: Ryder Lee <ryder.lee@mediatek.com>
@ -25,7 +25,7 @@
#include <linux/reset.h> #include <linux/reset.h>
#include "ahci.h" #include "ahci.h"
#define DRV_NAME "ahci" #define DRV_NAME "ahci-mtk"
#define SYS_CFG 0x14 #define SYS_CFG 0x14
#define SYS_CFG_SATA_MSK GENMASK(31, 30) #define SYS_CFG_SATA_MSK GENMASK(31, 30)
@ -192,5 +192,5 @@ static struct platform_driver mtk_ahci_driver = {
}; };
module_platform_driver(mtk_ahci_driver); module_platform_driver(mtk_ahci_driver);
MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver"); MODULE_DESCRIPTION("MediaTek SATA AHCI Driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");

12
drivers/ata/ahci_qoriq.c
View File

@ -35,6 +35,8 @@
/* port register default value */ /* port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe #define AHCI_PORT_PHY_1_CFG 0xa003fffe
#define AHCI_PORT_PHY2_CFG 0x28184d1f
#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029 #define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff #define AHCI_PORT_AXICC_CFG 0x3fffffff
@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
qpriv->ecc_addr); qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent) if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS2080A: case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent) if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
qpriv->ecc_addr); qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent) if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
qpriv->ecc_addr); qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent) if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS2088A: case AHCI_LS2088A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent) if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);

12
drivers/ata/libata-core.c
View File

@ -3082,13 +3082,19 @@ int sata_down_spd_limit(struct ata_link *link, u32 spd_limit)
bit = fls(mask) - 1; bit = fls(mask) - 1;
mask &= ~(1 << bit); mask &= ~(1 << bit);
/* Mask off all speeds higher than or equal to the current /*
* one. Force 1.5Gbps if current SPD is not available. * Mask off all speeds higher than or equal to the current one. At
* this point, if current SPD is not available and we previously
* recorded the link speed from SStatus, the driver has already
* masked off the highest bit so mask should already be 1 or 0.
* Otherwise, we should not force 1.5Gbps on a link where we have
* not previously recorded speed from SStatus. Just return in this
* case.
*/ */
if (spd > 1) if (spd > 1)
mask &= (1 << (spd - 1)) - 1; mask &= (1 << (spd - 1)) - 1;
else else
mask &= 1; return -EINVAL;
/* were we already at the bottom? */ /* were we already at the bottom? */
if (!mask) if (!mask)

16
drivers/ata/pata_pdc2027x.c
View File

@ -82,7 +82,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
* is issued to the device. However, if the controller clock is 133MHz, * is issued to the device. However, if the controller clock is 133MHz,
* the following tables must be used. * the following tables must be used.
*/ */
static struct pdc2027x_pio_timing { static const struct pdc2027x_pio_timing {
u8 value0, value1, value2; u8 value0, value1, value2;
} pdc2027x_pio_timing_tbl[] = { } pdc2027x_pio_timing_tbl[] = {
{ 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
@ -92,7 +92,7 @@ static struct pdc2027x_pio_timing {
{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
}; };
static struct pdc2027x_mdma_timing { static const struct pdc2027x_mdma_timing {
u8 value0, value1; u8 value0, value1;
} pdc2027x_mdma_timing_tbl[] = { } pdc2027x_mdma_timing_tbl[] = {
{ 0xdf, 0x5f }, /* MDMA mode 0 */ { 0xdf, 0x5f }, /* MDMA mode 0 */
@ -100,7 +100,7 @@ static struct pdc2027x_mdma_timing {
{ 0x69, 0x25 }, /* MDMA mode 2 */ { 0x69, 0x25 }, /* MDMA mode 2 */
}; };
static struct pdc2027x_udma_timing { static const struct pdc2027x_udma_timing {
u8 value0, value1, value2; u8 value0, value1, value2;
} pdc2027x_udma_timing_tbl[] = { } pdc2027x_udma_timing_tbl[] = {
{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
@ -649,7 +649,7 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
* @host: target ATA host * @host: target ATA host
* @board_idx: board identifier * @board_idx: board identifier
*/ */
static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
{ {
long pll_clock; long pll_clock;
@ -665,8 +665,6 @@ static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
/* Adjust PLL control register */ /* Adjust PLL control register */
pdc_adjust_pll(host, pll_clock, board_idx); pdc_adjust_pll(host, pll_clock, board_idx);
return 0;
} }
/** /**
@ -753,8 +751,7 @@ static int pdc2027x_init_one(struct pci_dev *pdev,
//pci_enable_intx(pdev); //pci_enable_intx(pdev);
/* initialize adapter */ /* initialize adapter */
if (pdc_hardware_init(host, board_idx) != 0) pdc_hardware_init(host, board_idx);
return -EIO;
pci_set_master(pdev); pci_set_master(pdev);
return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
@ -778,8 +775,7 @@ static int pdc2027x_reinit_one(struct pci_dev *pdev)
else else
board_idx = PDC_UDMA_133; board_idx = PDC_UDMA_133;
if (pdc_hardware_init(host, board_idx)) pdc_hardware_init(host, board_idx);
return -EIO;
ata_host_resume(host); ata_host_resume(host);
return 0; return 0;