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OMAPDSS: DSI: Fix PLL_SELFEQDCO field width 

PLL_SELFREQDCO bitfield is from bit 3 to 1, but the driver writes bits
from 4 to 1. The bit 4 is 'reserved', so this probably should not cause
any issues, but it's better to fix it.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen 2014-10-22 11:21:11 +03:00
parent aba837a280
commit a7f91edfdd
1 changed files with 1 additions and 1 deletions
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2
drivers/video/fbdev/omap2/dss/dsi.c
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@ -1603,7 +1603,7 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev,
} else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
}
l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */