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sparc32, sun4m: bugfix in SMP IPI traphandler 

Three new IPIs were introduced by commit
ecbc42b70a ("sparc32, sun4m:
Implemented SMP IPIs support for SUN4M machines"), the
old handler was already prepared for IPIs but handled only
IRQ14 and IRQ13, this patch adds support for the new IPI at
IRQ12.

The IPI trap handler looks at the mask rather than the
pending IRQ/IPI, this bug may have masked the problem
above, introduced by the same commit.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Daniel Hellstrom 2011-06-09 02:54:08 +00:00 committed by David S. Miller
parent 6cb79b3f3b
commit a7d82a0a3c
1 changed files with 2 additions and 2 deletions
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4
arch/sparc/kernel/entry.S
View File

@ -229,7 +229,7 @@ real_irq_entry:
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
.globl patchme_maybe_smp_msg .globl patchme_maybe_smp_msg
cmp %l7, 12 cmp %l7, 11
patchme_maybe_smp_msg: patchme_maybe_smp_msg:
bgu maybe_smp4m_msg bgu maybe_smp4m_msg
nop nop
@ -293,7 +293,7 @@ maybe_smp4m_msg:
WRITE_PAUSE WRITE_PAUSE
wr %l4, PSR_ET, %psr wr %l4, PSR_ET, %psr
WRITE_PAUSE WRITE_PAUSE
sll %o2, 28, %o2 ! shift for simpler checks below sll %o3, 28, %o2 ! shift for simpler checks below
maybe_smp4m_msg_check_single: maybe_smp4m_msg_check_single:
andcc %o2, 0x1, %g0 andcc %o2, 0x1, %g0
beq,a maybe_smp4m_msg_check_mask beq,a maybe_smp4m_msg_check_mask