ARM: shmobile: Add r8a73a4 CMT10 clock event
Add clock event support for CMT1 timer channel 0 to the r8a73a4 SoC code. The CMT is used together with a 32KHz clock in this case. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -505,7 +505,7 @@ static struct clk div6_clks[DIV6_NR] = {
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/* MSTP */
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enum {
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MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
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MSTP323, MSTP318, MSTP317, MSTP316,
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MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
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MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
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MSTP411, MSTP410, MSTP409,
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MSTP522, MSTP515,
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@ -529,6 +529,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */
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[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */
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[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */
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[MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
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[MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
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@ -593,6 +594,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
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CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
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CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
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CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
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CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
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CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
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@ -22,6 +22,7 @@
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#include <linux/of_platform.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a73a4.h>
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@ -168,6 +169,25 @@ static const struct resource thermal0_resources[] = {
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thermal0_resources, \
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ARRAY_SIZE(thermal0_resources))
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static struct resource cmt10_resources[] = {
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DEFINE_RES_MEM(0xe6130010, 0x0c),
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DEFINE_RES_MEM(0xe6130000, 0x04),
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DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
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};
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#define r8a7790_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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void __init r8a73a4_add_standard_devices(void)
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{
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r8a73a4_register_scif(SCIFA0);
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@ -179,6 +199,7 @@ void __init r8a73a4_add_standard_devices(void)
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r8a73a4_register_irqc(0);
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r8a73a4_register_irqc(1);
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r8a73a4_register_thermal();
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r8a7790_register_cmt(10);
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}
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#ifdef CONFIG_USE_OF
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