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ath9k: Fix PHY restart workaround 

The PHY restart workaround that handles baseband hangs
for packets with unsupported rates is required only
for a HW bug in AR9300 v2.2. All the subsequent chips in
the AR9003 family do not require this driver fix since
it has been addressed in the HW.

Since the value of the AR_PHY_RESTART register is written
with the default initvals, make sure that PHY restart is
always disabled once this particular BB hang signaure has
been encountered.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith Manoharan 2013-12-24 10:44:21 +05:30 committed by John W. Linville
parent 222e04830f
commit a7abaf7da9
2 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/net/wireless/ath/ath9k/ar9003_phy.c
View File

@ -1930,6 +1930,7 @@ EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
{
u8 result;
u32 val;
/* While receiving unsupported rate frame rx state machine
@ -1937,15 +1938,13 @@ void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
* state, BB would go hang. If RXSM is in 0xb state after
* first bb panic, ensure to disable the phy_restart.
*/
if (!((MS(ah->bb_watchdog_last_status,
AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
ah->bb_hang_rx_ofdm))
return;
result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
ah->bb_hang_rx_ofdm = true;
val = REG_READ(ah, AR_PHY_RESTART);
val &= ~AR_PHY_RESTART_ENA;
REG_WRITE(ah, AR_PHY_RESTART, val);
if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
ah->bb_hang_rx_ofdm = true;
val = REG_READ(ah, AR_PHY_RESTART);
val &= ~AR_PHY_RESTART_ENA;
REG_WRITE(ah, AR_PHY_RESTART, val);
}
}
EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);

5
drivers/net/wireless/ath/ath9k/hw.c
View File

@ -1935,10 +1935,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ath9k_hw_loadnf(ah, chan);
ath9k_hw_start_nfcal(ah, true);
if (AR_SREV_9300_20_OR_LATER(ah)) {
if (AR_SREV_9300_20_OR_LATER(ah))
ar9003_hw_bb_watchdog_config(ah);
if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
ar9003_hw_disable_phy_restart(ah);
}
ath9k_hw_apply_gpio_override(ah);