drm/tegra: Changes for v4.10-rc1
This has a couple of fixes for IOMMU support and some fixes for error handling. -----BEGIN PGP SIGNATURE----- iQIwBAABCAAaBQJYSrsDExx0cmVkaW5nQG52aWRpYS5jb20ACgkQ3SOs138+s6Hp VA//Z2ndM65bUsyUlajewYgDcEtsVpHRa9obrX/d1/3Uj428AMFhTsRIE70NCikc hmbpeg3pUwZefD5Ut8BCz+H95Exlg4F5NpNNaGqu1u09LHBP15hRstbf2VLaIf+r p0pfdsD2Mk9w3z3F6OJEvAno8J3IVN9J62BR0Npb4bM/uFbORu2UCMUWpwDJsEsc +5TbTgdNkMGnENMr4IqDmLvYycngYBXcyFtN9vnH2Jmfki/WSb47Qqhd0xmLh4La jzFbFnbHqyPnmGtOnxK29Zx27lOqk/zoX8ei3Wl+lu+aETYAoC+diau99KJW7LkP wQnI8iSCqHapm/so/GtWRPpUSuy86Wz1z+JiVHN2fcCXyiNRFY4B7n+ECHJMix8w ZVLU/nQsmTec/U2XNMsG1UGRXoL9YJebyawLgO+mZo24u/Au63LnW/fQQHzh1b4E pTbewp1xSu9zrayZNvew6F8PaiVhTnKzbXouyrSWO9Wee/Kvr2X6kAuYuK/XYcif GqSME9jhsXmvc4YO/Xtq3QbisEyVmQI3v+5q8Xx7zeJfPWqXvENBVmHfyvl+KXQo 1qX8xZv3rX8jE5uLrJyD/YjPVsvILRzXiL5ms2Vsa+D+nd05aQfnWeieqP+R8qkV MHevcCaEXGG97yQCHRAle8r+0Z7OTr5WVrAYHeCkwzWgJz0= =sDMr -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-4.10-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.10-rc1 This has a couple of fixes for IOMMU support and some fixes for error handling. * tag 'drm/tegra/for-4.10-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: Set sgt pointer in BO pin drm/tegra: Support kernel mappings with IOMMU gpu: host1x: Add locking to syncpt gpu: host1x: Store device address to all bufs drm/tegra: gem: Remove some dead code drm/tegra: sor: No need to free devm_ allocated memory drm/tegra: Fix error handling drm/tegra: dpaux: Fix error handling
This commit is contained in:
commit
a77a1ad11e
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@ -539,9 +539,9 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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dpaux->desc.owner = THIS_MODULE;
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dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
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if (!dpaux->pinctrl) {
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if (IS_ERR(dpaux->pinctrl)) {
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dev_err(&pdev->dev, "failed to register pincontrol\n");
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return -ENODEV;
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return PTR_ERR(dpaux->pinctrl);
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}
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#endif
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/* enable and clear all interrupts */
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@ -2,7 +2,7 @@
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* NVIDIA Tegra DRM GEM helper functions
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*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix
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* Copyright (C) 2013 NVIDIA CORPORATION, All rights reserved.
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* Copyright (C) 2013-2015 NVIDIA CORPORATION, All rights reserved.
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*
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* Based on the GEM/CMA helpers
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*
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@ -36,6 +36,8 @@ static dma_addr_t tegra_bo_pin(struct host1x_bo *bo, struct sg_table **sgt)
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{
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struct tegra_bo *obj = host1x_to_tegra_bo(bo);
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*sgt = obj->sgt;
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return obj->paddr;
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}
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@ -47,23 +49,51 @@ static void *tegra_bo_mmap(struct host1x_bo *bo)
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{
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struct tegra_bo *obj = host1x_to_tegra_bo(bo);
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return obj->vaddr;
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if (obj->vaddr)
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return obj->vaddr;
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else if (obj->gem.import_attach)
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return dma_buf_vmap(obj->gem.import_attach->dmabuf);
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else
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return vmap(obj->pages, obj->num_pages, VM_MAP,
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pgprot_writecombine(PAGE_KERNEL));
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}
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static void tegra_bo_munmap(struct host1x_bo *bo, void *addr)
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{
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struct tegra_bo *obj = host1x_to_tegra_bo(bo);
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if (obj->vaddr)
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return;
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else if (obj->gem.import_attach)
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dma_buf_vunmap(obj->gem.import_attach->dmabuf, addr);
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else
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vunmap(addr);
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}
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static void *tegra_bo_kmap(struct host1x_bo *bo, unsigned int page)
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{
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struct tegra_bo *obj = host1x_to_tegra_bo(bo);
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return obj->vaddr + page * PAGE_SIZE;
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if (obj->vaddr)
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return obj->vaddr + page * PAGE_SIZE;
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else if (obj->gem.import_attach)
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return dma_buf_kmap(obj->gem.import_attach->dmabuf, page);
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else
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return vmap(obj->pages + page, 1, VM_MAP,
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pgprot_writecombine(PAGE_KERNEL));
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}
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static void tegra_bo_kunmap(struct host1x_bo *bo, unsigned int page,
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void *addr)
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{
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struct tegra_bo *obj = host1x_to_tegra_bo(bo);
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if (obj->vaddr)
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return;
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else if (obj->gem.import_attach)
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dma_buf_kunmap(obj->gem.import_attach->dmabuf, page, addr);
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else
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vunmap(addr);
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}
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static struct host1x_bo *tegra_bo_get(struct host1x_bo *bo)
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@ -318,11 +348,6 @@ static struct tegra_bo *tegra_bo_import(struct drm_device *drm,
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get_dma_buf(buf);
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bo->sgt = dma_buf_map_attachment(attach, DMA_TO_DEVICE);
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if (!bo->sgt) {
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err = -ENOMEM;
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goto detach;
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}
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if (IS_ERR(bo->sgt)) {
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err = PTR_ERR(bo->sgt);
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goto detach;
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@ -268,9 +268,9 @@ static int gr3d_probe(struct platform_device *pdev)
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if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
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gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
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if (IS_ERR(gr3d->clk)) {
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if (IS_ERR(gr3d->clk_secondary)) {
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dev_err(&pdev->dev, "cannot get secondary clock\n");
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return PTR_ERR(gr3d->clk);
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return PTR_ERR(gr3d->clk_secondary);
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}
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gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
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@ -349,8 +349,6 @@ static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor,
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brick->hw.init = &init;
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clk = devm_clk_register(sor->dev, &brick->hw);
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if (IS_ERR(clk))
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kfree(brick);
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return clk;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2013, NVIDIA Corporation.
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* Copyright (c) 2012-2015, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -120,6 +120,7 @@ struct host1x {
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struct host1x_syncpt *nop_sp;
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struct mutex syncpt_mutex;
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struct mutex chlist_mutex;
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struct host1x_channel chlist;
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unsigned long allocated_channels;
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@ -1,7 +1,7 @@
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/*
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* Tegra host1x Job
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*
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* Copyright (c) 2010-2013, NVIDIA Corporation.
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* Copyright (c) 2010-2015, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -539,9 +539,12 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev)
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g->base = job->gather_addr_phys[i];
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for (j = i + 1; j < job->num_gathers; j++)
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if (job->gathers[j].bo == g->bo)
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for (j = i + 1; j < job->num_gathers; j++) {
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if (job->gathers[j].bo == g->bo) {
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job->gathers[j].handled = true;
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job->gathers[j].base = g->base;
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}
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}
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err = do_relocs(job, g->bo);
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if (err)
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@ -1,7 +1,7 @@
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/*
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* Tegra host1x Syncpoints
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*
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* Copyright (c) 2010-2013, NVIDIA Corporation.
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* Copyright (c) 2010-2015, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -61,22 +61,24 @@ static struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
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struct host1x_syncpt *sp = host->syncpt;
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char *name;
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mutex_lock(&host->syncpt_mutex);
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for (i = 0; i < host->info->nb_pts && sp->name; i++, sp++)
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;
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if (i >= host->info->nb_pts)
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return NULL;
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goto unlock;
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if (flags & HOST1X_SYNCPT_HAS_BASE) {
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sp->base = host1x_syncpt_base_request(host);
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if (!sp->base)
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return NULL;
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goto unlock;
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}
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name = kasprintf(GFP_KERNEL, "%02u-%s", sp->id,
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dev ? dev_name(dev) : NULL);
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if (!name)
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return NULL;
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goto free_base;
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sp->dev = dev;
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sp->name = name;
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else
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sp->client_managed = false;
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mutex_unlock(&host->syncpt_mutex);
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return sp;
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free_base:
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host1x_syncpt_base_free(sp->base);
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sp->base = NULL;
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unlock:
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mutex_unlock(&host->syncpt_mutex);
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return NULL;
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}
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u32 host1x_syncpt_id(struct host1x_syncpt *sp)
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@ -378,6 +388,7 @@ int host1x_syncpt_init(struct host1x *host)
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for (i = 0; i < host->info->nb_bases; i++)
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bases[i].id = i;
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mutex_init(&host->syncpt_mutex);
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host->syncpt = syncpt;
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host->bases = bases;
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@ -405,12 +416,16 @@ void host1x_syncpt_free(struct host1x_syncpt *sp)
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if (!sp)
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return;
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mutex_lock(&sp->host->syncpt_mutex);
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host1x_syncpt_base_free(sp->base);
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kfree(sp->name);
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sp->base = NULL;
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sp->dev = NULL;
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sp->name = NULL;
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sp->client_managed = false;
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mutex_unlock(&sp->host->syncpt_mutex);
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}
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EXPORT_SYMBOL(host1x_syncpt_free);
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