avr32: Remove include/asm-avr32/arch-at32ap
Since all users have been converted over to use <mach/foo.h>, there's no need for the arch-at32ap directory and associated symlink anymore. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
parent
a09e64fbc0
commit
a7448db482
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@ -39,20 +39,6 @@ core-y += arch/avr32/mm/
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drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
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libs-y += arch/avr32/lib/
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archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
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include/asm-avr32/.arch: $(wildcard include/config/platform/*.h) include/config/auto.conf
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@echo ' SYMLINK include/asm-avr32/arch -> include/asm-avr32/$(archincdir-y)'
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ifneq ($(KBUILD_SRC),)
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$(Q)mkdir -p include/asm-avr32
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$(Q)ln -fsn $(srctree)/include/asm-avr32/$(archincdir-y) include/asm-avr32/arch
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else
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$(Q)ln -fsn $(archincdir-y) include/asm-avr32/arch
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endif
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@touch $@
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archprepare: include/asm-avr32/.arch
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CLEAN_FILES += include/asm-avr32/.arch include/asm-avr32/arch
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BOOT_TARGETS := vmlinux.elf vmlinux.bin uImage uImage.srec
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@ -1,49 +0,0 @@
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/*
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* Pin definitions for AT32AP7000.
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_AT32AP700X_H__
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#define __ASM_ARCH_AT32AP700X_H__
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#define GPIO_PERIPH_A 0
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#define GPIO_PERIPH_B 1
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/*
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* Pin numbers identifying specific GPIO pins on the chip. They can
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* also be converted to IRQ numbers by passing them through
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* gpio_to_irq().
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*/
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#define GPIO_PIOA_BASE (0)
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#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
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#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
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#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
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#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
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#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
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#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
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#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
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#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
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#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
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/*
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* DMAC peripheral hardware handshaking interfaces, used with dw_dmac
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*/
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#define DMAC_MCI_RX 0
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#define DMAC_MCI_TX 1
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#define DMAC_DAC_TX 2
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#define DMAC_AC97_A_RX 3
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#define DMAC_AC97_A_TX 4
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#define DMAC_AC97_B_RX 5
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#define DMAC_AC97_B_TX 6
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#define DMAC_DMAREQ_0 7
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#define DMAC_DMAREQ_1 8
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#define DMAC_DMAREQ_2 9
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#define DMAC_DMAREQ_3 10
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#endif /* __ASM_ARCH_AT32AP700X_H__ */
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@ -1,121 +0,0 @@
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/*
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* Platform data definitions.
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*/
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#ifndef __ASM_ARCH_BOARD_H
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#define __ASM_ARCH_BOARD_H
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#include <linux/types.h>
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#define GPIO_PIN_NONE (-1)
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/*
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* Clock rates for various on-board oscillators. The number of entries
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* in this array is chip-dependent.
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*/
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extern unsigned long at32_board_osc_rates[];
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/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
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void at32_add_system_devices(void);
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#define ATMEL_MAX_UART 4
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extern struct platform_device *atmel_default_console_device;
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struct atmel_uart_data {
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short use_dma_tx; /* use transmit DMA? */
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short use_dma_rx; /* use receive DMA? */
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void __iomem *regs; /* virtual base address, if any */
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};
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void at32_map_usart(unsigned int hw_id, unsigned int line);
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struct platform_device *at32_add_device_usart(unsigned int id);
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struct eth_platform_data {
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u32 phy_mask;
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u8 is_rmii;
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};
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struct platform_device *
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at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
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struct spi_board_info;
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struct platform_device *
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at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
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struct atmel_lcdfb_info;
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struct platform_device *
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at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
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unsigned long fbmem_start, unsigned long fbmem_len,
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unsigned int pin_config);
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struct usba_platform_data;
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struct platform_device *
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at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
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struct ide_platform_data {
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u8 cs;
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};
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struct platform_device *
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at32_add_device_ide(unsigned int id, unsigned int extint,
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struct ide_platform_data *data);
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/* mask says which PWM channels to mux */
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struct platform_device *at32_add_device_pwm(u32 mask);
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/* depending on what's hooked up, not all SSC pins will be used */
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#define ATMEL_SSC_TK 0x01
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#define ATMEL_SSC_TF 0x02
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#define ATMEL_SSC_TD 0x04
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#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
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#define ATMEL_SSC_RK 0x10
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#define ATMEL_SSC_RF 0x20
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#define ATMEL_SSC_RD 0x40
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#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
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struct platform_device *
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at32_add_device_ssc(unsigned int id, unsigned int flags);
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struct i2c_board_info;
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struct platform_device *at32_add_device_twi(unsigned int id,
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struct i2c_board_info *b,
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unsigned int n);
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struct mci_platform_data;
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struct platform_device *
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at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
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struct ac97c_platform_data {
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unsigned short dma_rx_periph_id;
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unsigned short dma_tx_periph_id;
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unsigned short dma_controller_id;
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int reset_pin;
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};
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struct platform_device *
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at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data);
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struct platform_device *at32_add_device_abdac(unsigned int id);
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struct platform_device *at32_add_device_psif(unsigned int id);
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struct cf_platform_data {
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int detect_pin;
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int reset_pin;
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int vcc_pin;
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int ready_pin;
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u8 cs;
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};
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struct platform_device *
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at32_add_device_cf(unsigned int id, unsigned int extint,
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struct cf_platform_data *data);
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/* NAND / SmartMedia */
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struct atmel_nand_data {
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int enable_pin; /* chip enable */
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int det_pin; /* card detect */
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int rdy_pin; /* ready/busy */
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u8 ale; /* address line number connected to ALE */
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u8 cle; /* address line number connected to CLE */
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u8 bus_width_16; /* buswidth is 16 bit */
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struct mtd_partition *(*partition_info)(int size, int *num_partitions);
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};
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struct platform_device *
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at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
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#endif /* __ASM_ARCH_BOARD_H */
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@ -1,35 +0,0 @@
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/*
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* AVR32 and (fake) AT91 CPU identification
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_CPU_H
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#define __ASM_ARCH_CPU_H
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/*
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* Only AT32AP7000 is defined for now. We can identify the specific
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* chip at runtime, but I'm not sure if it's really worth it.
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*/
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#ifdef CONFIG_CPU_AT32AP700X
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# define cpu_is_at32ap7000() (1)
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#else
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# define cpu_is_at32ap7000() (0)
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#endif
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/*
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* Since this is AVR32, we will never run on any AT91 CPU. But these
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* definitions may reduce clutter in common drivers.
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*/
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#define cpu_is_at91rm9200() (0)
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#define cpu_is_at91sam9xe() (0)
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#define cpu_is_at91sam9260() (0)
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#define cpu_is_at91sam9261() (0)
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#define cpu_is_at91sam9263() (0)
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#define cpu_is_at91sam9rl() (0)
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#define cpu_is_at91cap9() (0)
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#endif /* __ASM_ARCH_CPU_H */
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@ -1,45 +0,0 @@
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#ifndef __ASM_AVR32_ARCH_GPIO_H
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#define __ASM_AVR32_ARCH_GPIO_H
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#include <linux/compiler.h>
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#include <asm/irq.h>
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/* Some GPIO chips can manage IRQs; some can't. The exact numbers can
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* be changed if needed, but for the moment they're not configurable.
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*/
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#define ARCH_NR_GPIOS (NR_GPIO_IRQS + 2 * 32)
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/* Arch-neutral GPIO API, supporting both "native" and external GPIOs. */
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#include <asm-generic/gpio.h>
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static inline int gpio_get_value(unsigned int gpio)
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{
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return __gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned int gpio, int value)
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{
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__gpio_set_value(gpio, value);
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}
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static inline int gpio_cansleep(unsigned int gpio)
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{
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return __gpio_cansleep(gpio);
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}
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static inline int gpio_to_irq(unsigned int gpio)
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{
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if (gpio < NR_GPIO_IRQS)
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return gpio + GPIO_IRQ_BASE;
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return -EINVAL;
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}
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static inline int irq_to_gpio(unsigned int irq)
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{
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return irq - GPIO_IRQ_BASE;
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}
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#endif /* __ASM_AVR32_ARCH_GPIO_H */
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@ -1,18 +0,0 @@
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/*
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* AT32AP platform initialization calls.
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_AT32AP_INIT_H__
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#define __ASM_AVR32_AT32AP_INIT_H__
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void setup_platform(void);
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void setup_board(void);
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void at32_setup_serial_console(unsigned int usart_id);
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#endif /* __ASM_AVR32_AT32AP_INIT_H__ */
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@ -1,39 +0,0 @@
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#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
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#define __ASM_AVR32_ARCH_AT32AP_IO_H
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/* For "bizarre" halfword swapping */
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#include <linux/byteorder/swabb.h>
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#if defined(CONFIG_AP700X_32_BIT_SMC)
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# define __swizzle_addr_b(addr) (addr ^ 3UL)
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# define __swizzle_addr_w(addr) (addr ^ 2UL)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define ioswabl(a, x) (x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) swab16(x)
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# define __mem_ioswabl(a, x) swab32(x)
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#elif defined(CONFIG_AP700X_16_BIT_SMC)
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# define __swizzle_addr_b(addr) (addr ^ 1UL)
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# define __swizzle_addr_w(addr) (addr)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define ioswabl(a, x) swahw32(x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) swab16(x)
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# define __mem_ioswabl(a, x) swahb32(x)
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#else
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# define __swizzle_addr_b(addr) (addr)
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# define __swizzle_addr_w(addr) (addr)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) swab16(x)
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# define ioswabl(a, x) swab32(x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) (x)
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# define __mem_ioswabl(a, x) (x)
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#endif
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#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
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@ -1,14 +0,0 @@
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#ifndef __ASM_AVR32_ARCH_IRQ_H
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#define __ASM_AVR32_ARCH_IRQ_H
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#define EIM_IRQ_BASE NR_INTERNAL_IRQS
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#define NR_EIM_IRQS 32
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#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
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#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
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#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/)
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#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)
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#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)
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#endif /* __ASM_AVR32_ARCH_IRQ_H */
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@ -1,51 +0,0 @@
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/*
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* AVR32 AP Power Management.
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_ARCH_PM_H
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#define __ASM_AVR32_ARCH_PM_H
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/* Possible arguments to the "sleep" instruction */
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#define CPU_SLEEP_IDLE 0
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#define CPU_SLEEP_FROZEN 1
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#define CPU_SLEEP_STANDBY 2
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#define CPU_SLEEP_STOP 3
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#define CPU_SLEEP_STATIC 5
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#ifndef __ASSEMBLY__
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extern void cpu_enter_idle(void);
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extern void cpu_enter_standby(unsigned long sdramc_base);
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extern bool disable_idle_sleep;
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static inline void cpu_disable_idle_sleep(void)
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{
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disable_idle_sleep = true;
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}
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static inline void cpu_enable_idle_sleep(void)
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{
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disable_idle_sleep = false;
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}
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static inline void cpu_idle_sleep(void)
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{
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/*
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* If we're using the COUNT and COMPARE registers for
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* timekeeping, we can't use the IDLE state.
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*/
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if (disable_idle_sleep)
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cpu_relax();
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else
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cpu_enter_idle();
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}
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void intc_set_suspend_handler(unsigned long offset);
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#endif
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#endif /* __ASM_AVR32_ARCH_PM_H */
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@ -1,29 +0,0 @@
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/*
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* AT32 portmux interface.
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*
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* Copyright (C) 2006 Atmel Corporation
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
|
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*/
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#ifndef __ASM_ARCH_PORTMUX_H__
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#define __ASM_ARCH_PORTMUX_H__
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/*
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* Set up pin multiplexing, called from board init only.
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*
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* The following flags determine the initial state of the pin.
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*/
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#define AT32_GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
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#define AT32_GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
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#define AT32_GPIOF_HIGH 0x00000004 /* (OUT) Set output high */
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#define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */
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#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */
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void at32_select_periph(unsigned int pin, unsigned int periph,
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unsigned long flags);
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void at32_select_gpio(unsigned int pin, unsigned long flags);
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void at32_reserve_pin(unsigned int pin);
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#endif /* __ASM_ARCH_PORTMUX_H__ */
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@ -1,113 +0,0 @@
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/*
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* Static Memory Controller for AT32 chips
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*
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||||
* Copyright (C) 2006 Atmel Corporation
|
||||
*
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||||
* Inspired by the OMAP2 General-Purpose Memory Controller interface
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*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __ARCH_AT32AP_SMC_H
|
||||
#define __ARCH_AT32AP_SMC_H
|
||||
|
||||
/*
|
||||
* All timing parameters are in nanoseconds.
|
||||
*/
|
||||
struct smc_timing {
|
||||
/* Delay from address valid to assertion of given strobe */
|
||||
int ncs_read_setup;
|
||||
int nrd_setup;
|
||||
int ncs_write_setup;
|
||||
int nwe_setup;
|
||||
|
||||
/* Pulse length of given strobe */
|
||||
int ncs_read_pulse;
|
||||
int nrd_pulse;
|
||||
int ncs_write_pulse;
|
||||
int nwe_pulse;
|
||||
|
||||
/* Total cycle length of given operation */
|
||||
int read_cycle;
|
||||
int write_cycle;
|
||||
|
||||
/* Minimal recovery times, will extend cycle if needed */
|
||||
int ncs_read_recover;
|
||||
int nrd_recover;
|
||||
int ncs_write_recover;
|
||||
int nwe_recover;
|
||||
};
|
||||
|
||||
/*
|
||||
* All timing parameters are in clock cycles.
|
||||
*/
|
||||
struct smc_config {
|
||||
|
||||
/* Delay from address valid to assertion of given strobe */
|
||||
u8 ncs_read_setup;
|
||||
u8 nrd_setup;
|
||||
u8 ncs_write_setup;
|
||||
u8 nwe_setup;
|
||||
|
||||
/* Pulse length of given strobe */
|
||||
u8 ncs_read_pulse;
|
||||
u8 nrd_pulse;
|
||||
u8 ncs_write_pulse;
|
||||
u8 nwe_pulse;
|
||||
|
||||
/* Total cycle length of given operation */
|
||||
u8 read_cycle;
|
||||
u8 write_cycle;
|
||||
|
||||
/* Bus width in bytes */
|
||||
u8 bus_width;
|
||||
|
||||
/*
|
||||
* 0: Data is sampled on rising edge of NCS
|
||||
* 1: Data is sampled on rising edge of NRD
|
||||
*/
|
||||
unsigned int nrd_controlled:1;
|
||||
|
||||
/*
|
||||
* 0: Data is driven on falling edge of NCS
|
||||
* 1: Data is driven on falling edge of NWR
|
||||
*/
|
||||
unsigned int nwe_controlled:1;
|
||||
|
||||
/*
|
||||
* 0: NWAIT is disabled
|
||||
* 1: Reserved
|
||||
* 2: NWAIT is frozen mode
|
||||
* 3: NWAIT in ready mode
|
||||
*/
|
||||
unsigned int nwait_mode:2;
|
||||
|
||||
/*
|
||||
* 0: Byte select access type
|
||||
* 1: Byte write access type
|
||||
*/
|
||||
unsigned int byte_write:1;
|
||||
|
||||
/*
|
||||
* Number of clock cycles before data is released after
|
||||
* the rising edge of the read controlling signal
|
||||
*
|
||||
* Total cycles from SMC is tdf_cycles + 1
|
||||
*/
|
||||
unsigned int tdf_cycles:4;
|
||||
|
||||
/*
|
||||
* 0: TDF optimization disabled
|
||||
* 1: TDF optimization enabled
|
||||
*/
|
||||
unsigned int tdf_mode:1;
|
||||
};
|
||||
|
||||
extern void smc_set_timing(struct smc_config *config,
|
||||
const struct smc_timing *timing);
|
||||
|
||||
extern int smc_set_configuration(int cs, const struct smc_config *config);
|
||||
extern struct smc_config *smc_get_configuration(int cs);
|
||||
|
||||
#endif /* __ARCH_AT32AP_SMC_H */
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* Simple SRAM allocator
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __ASM_AVR32_ARCH_SRAM_H
|
||||
#define __ASM_AVR32_ARCH_SRAM_H
|
||||
|
||||
#include <linux/genalloc.h>
|
||||
|
||||
extern struct gen_pool *sram_pool;
|
||||
|
||||
static inline unsigned long sram_alloc(size_t len)
|
||||
{
|
||||
if (!sram_pool)
|
||||
return 0UL;
|
||||
|
||||
return gen_pool_alloc(sram_pool, len);
|
||||
}
|
||||
|
||||
static inline void sram_free(unsigned long addr, size_t len)
|
||||
{
|
||||
return gen_pool_free(sram_pool, addr, len);
|
||||
}
|
||||
|
||||
#endif /* __ASM_AVR32_ARCH_SRAM_H */
|
||||
Loading…
Reference in New Issue