powerpc/85xx: add sysfs for pw20 state and altivec idle
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~48(ns): TB[63]
49~97(ns): TB[62]
98~195(ns): TB[61]
196~390(ns): TB[60]
391~780(ns): TB[59]
781~1560(ns): TB[58]
...
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
[scottwood@freescale.com: change ifdef]
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Wang Dongsheng
Scott Wood
parent
1d47ddf7c3
commit
a7189483f0
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@ -86,6 +86,304 @@ __setup("smt-snooze-delay=", setup_smt_snooze_delay);
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#endif /* CONFIG_PPC64 */
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#ifdef CONFIG_PPC_FSL_BOOK3E
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#define MAX_BIT 63
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static u64 pw20_wt;
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static u64 altivec_idle_wt;
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static unsigned int get_idle_ticks_bit(u64 ns)
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{
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u64 cycle;
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if (ns >= 10000)
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cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
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else
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cycle = div_u64(ns * tb_ticks_per_usec, 1000);
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if (!cycle)
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return 0;
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return ilog2(cycle);
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}
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static void do_show_pwrmgtcr0(void *val)
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{
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u32 *value = val;
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*value = mfspr(SPRN_PWRMGTCR0);
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}
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static ssize_t show_pw20_state(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 value;
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unsigned int cpu = dev->id;
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smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
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value &= PWRMGTCR0_PW20_WAIT;
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return sprintf(buf, "%u\n", value ? 1 : 0);
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}
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static void do_store_pw20_state(void *val)
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{
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u32 *value = val;
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u32 pw20_state;
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pw20_state = mfspr(SPRN_PWRMGTCR0);
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if (*value)
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pw20_state |= PWRMGTCR0_PW20_WAIT;
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else
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pw20_state &= ~PWRMGTCR0_PW20_WAIT;
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mtspr(SPRN_PWRMGTCR0, pw20_state);
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}
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static ssize_t store_pw20_state(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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u32 value;
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unsigned int cpu = dev->id;
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if (kstrtou32(buf, 0, &value))
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return -EINVAL;
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if (value > 1)
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return -EINVAL;
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smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
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return count;
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}
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static ssize_t show_pw20_wait_time(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 value;
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u64 tb_cycle = 1;
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u64 time;
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unsigned int cpu = dev->id;
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if (!pw20_wt) {
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smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
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value = (value & PWRMGTCR0_PW20_ENT) >>
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PWRMGTCR0_PW20_ENT_SHIFT;
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tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
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/* convert ms to ns */
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if (tb_ticks_per_usec > 1000) {
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time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
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} else {
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u32 rem_us;
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time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
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&rem_us);
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time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
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}
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} else {
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time = pw20_wt;
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}
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return sprintf(buf, "%llu\n", time > 0 ? time : 0);
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}
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static void set_pw20_wait_entry_bit(void *val)
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{
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u32 *value = val;
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u32 pw20_idle;
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pw20_idle = mfspr(SPRN_PWRMGTCR0);
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/* Set Automatic PW20 Core Idle Count */
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/* clear count */
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pw20_idle &= ~PWRMGTCR0_PW20_ENT;
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/* set count */
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pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
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mtspr(SPRN_PWRMGTCR0, pw20_idle);
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}
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static ssize_t store_pw20_wait_time(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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u32 entry_bit;
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u64 value;
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unsigned int cpu = dev->id;
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if (kstrtou64(buf, 0, &value))
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return -EINVAL;
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if (!value)
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return -EINVAL;
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entry_bit = get_idle_ticks_bit(value);
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if (entry_bit > MAX_BIT)
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return -EINVAL;
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pw20_wt = value;
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smp_call_function_single(cpu, set_pw20_wait_entry_bit,
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&entry_bit, 1);
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return count;
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}
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static ssize_t show_altivec_idle(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 value;
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unsigned int cpu = dev->id;
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smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
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value &= PWRMGTCR0_AV_IDLE_PD_EN;
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return sprintf(buf, "%u\n", value ? 1 : 0);
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}
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static void do_store_altivec_idle(void *val)
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{
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u32 *value = val;
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u32 altivec_idle;
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altivec_idle = mfspr(SPRN_PWRMGTCR0);
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if (*value)
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altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
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else
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altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
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mtspr(SPRN_PWRMGTCR0, altivec_idle);
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}
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static ssize_t store_altivec_idle(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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u32 value;
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unsigned int cpu = dev->id;
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if (kstrtou32(buf, 0, &value))
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return -EINVAL;
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if (value > 1)
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return -EINVAL;
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smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
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return count;
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}
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static ssize_t show_altivec_idle_wait_time(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 value;
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u64 tb_cycle = 1;
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u64 time;
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unsigned int cpu = dev->id;
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if (!altivec_idle_wt) {
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smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
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value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
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PWRMGTCR0_AV_IDLE_CNT_SHIFT;
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tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
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/* convert ms to ns */
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if (tb_ticks_per_usec > 1000) {
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time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
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} else {
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u32 rem_us;
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time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
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&rem_us);
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time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
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}
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} else {
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time = altivec_idle_wt;
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}
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return sprintf(buf, "%llu\n", time > 0 ? time : 0);
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}
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static void set_altivec_idle_wait_entry_bit(void *val)
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{
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u32 *value = val;
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u32 altivec_idle;
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altivec_idle = mfspr(SPRN_PWRMGTCR0);
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/* Set Automatic AltiVec Idle Count */
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/* clear count */
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altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
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/* set count */
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altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
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mtspr(SPRN_PWRMGTCR0, altivec_idle);
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}
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static ssize_t store_altivec_idle_wait_time(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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u32 entry_bit;
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u64 value;
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unsigned int cpu = dev->id;
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if (kstrtou64(buf, 0, &value))
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return -EINVAL;
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if (!value)
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return -EINVAL;
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entry_bit = get_idle_ticks_bit(value);
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if (entry_bit > MAX_BIT)
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return -EINVAL;
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altivec_idle_wt = value;
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smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
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&entry_bit, 1);
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return count;
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}
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/*
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* Enable/Disable interface:
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* 0, disable. 1, enable.
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*/
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static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
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static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
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/*
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* Set wait time interface:(Nanosecond)
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* Example: Base on TBfreq is 41MHZ.
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* 1~48(ns): TB[63]
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* 49~97(ns): TB[62]
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* 98~195(ns): TB[61]
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* 196~390(ns): TB[60]
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* 391~780(ns): TB[59]
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* 781~1560(ns): TB[58]
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* ...
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*/
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static DEVICE_ATTR(pw20_wait_time, 0600,
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show_pw20_wait_time,
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store_pw20_wait_time);
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static DEVICE_ATTR(altivec_idle_wait_time, 0600,
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show_altivec_idle_wait_time,
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store_altivec_idle_wait_time);
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#endif
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/*
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* Enabling PMCs will slow partition context switch times so we only do
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* it the first time we write to the PMCs.
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@ -425,6 +723,15 @@ static void register_cpu_online(unsigned int cpu)
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device_create_file(s, &dev_attr_pir);
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#endif /* CONFIG_PPC64 */
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#ifdef CONFIG_PPC_FSL_BOOK3E
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if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
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device_create_file(s, &dev_attr_pw20_state);
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device_create_file(s, &dev_attr_pw20_wait_time);
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device_create_file(s, &dev_attr_altivec_idle);
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device_create_file(s, &dev_attr_altivec_idle_wait_time);
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}
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#endif
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cacheinfo_cpu_online(cpu);
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}
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@ -497,6 +804,15 @@ static void unregister_cpu_online(unsigned int cpu)
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device_remove_file(s, &dev_attr_pir);
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#endif /* CONFIG_PPC64 */
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#ifdef CONFIG_PPC_FSL_BOOK3E
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if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
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device_remove_file(s, &dev_attr_pw20_state);
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device_remove_file(s, &dev_attr_pw20_wait_time);
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device_remove_file(s, &dev_attr_altivec_idle);
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device_remove_file(s, &dev_attr_altivec_idle_wait_time);
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}
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#endif
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cacheinfo_cpu_offline(cpu);
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}
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