The imx fixes for 3.10:
* A few imx6 clock fixes. Nothing is extremely important, but since we're still in early -rc, I send them for 3.10 inclusion. * Having bootloader handle ARM errata, we will need to replicate the diagnostic register of boot cpu into secondary cores, since bootloader only sets up boot cpu. Otherwise, errata workaround simply does not work. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRkfdQAAoJEFBXWFqHsHzOOvoIAI5hte/C9p9H+aH0qAb7cE3d 5dhALwu72mUpoMgwH0tBA5eVcmqPJXwQSDJFigG5iqs6RLf7VOsGkWdd5mPZEn6i l4yqJ9ox4GmAo4WioQiiGCWzITfGbHqjd4ClfXtDmpThGvvrGquH/K9SxKtc4Jc+ Oa61dmOLgPc6XP78Q1zXB7rk9fcg1eL7IZQ+gTMEyDTPeJw2a5ILd/gwp8CffDkI VlMyWXrSu7ZZdmy6kaAlWZ9TouIi8aBedBnuuvD+k88Doua7Ar4PZ03dc2QOPwKb TRIKeOtvelWI3M8jJKQrhS/weQJqgsFvT3AgTZHSFHtaKioLfnaYLJf8puMpswM= =4IPh -----END PGP SIGNATURE----- Merge tag 'imx-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes From Shawn Guo, imx fixes for 3.10: - A few imx6 clock fixes. Nothing is extremely important, but since we're still in early -rc, I send them for 3.10 inclusion. - Having bootloader handle ARM errata, we will need to replicate the diagnostic register of boot cpu into secondary cores, since bootloader only sets up boot cpu. Otherwise, errata workaround simply does not work. * tag 'imx-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx: fix typo in gpu3d_shader_sels ARM: imx: replicate the diagnostic register of boot cpu into secondary cores ARM i.MX6: correct MLB clock configuration ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a706d8505c
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@ -177,7 +177,8 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
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static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
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static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
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static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
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static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", };
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static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
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static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
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@ -185,7 +186,7 @@ static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd
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static const char *gpu_axi_sels[] = { "axi", "ahb", };
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static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
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static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
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static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
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static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
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static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
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static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
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static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
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@ -369,8 +370,8 @@ int __init mx6q_clocks_init(void)
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clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
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clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
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clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
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clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
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clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
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clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
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clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
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clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
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clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
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clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
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@ -498,7 +499,7 @@ int __init mx6q_clocks_init(void)
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clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
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clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
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clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
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clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18);
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clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
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clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
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clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
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clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
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@ -18,8 +18,20 @@
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.section ".text.head", "ax"
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#ifdef CONFIG_SMP
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diag_reg_offset:
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.word g_diag_reg - .
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.macro set_diag_reg
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adr r0, diag_reg_offset
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ldr r1, [r0]
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add r1, r1, r0 @ r1 = physical &g_diag_reg
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ldr r0, [r1]
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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.endm
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ENTRY(v7_secondary_startup)
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bl v7_invalidate_l1
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set_diag_reg
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b secondary_startup
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ENDPROC(v7_secondary_startup)
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#endif
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@ -12,6 +12,7 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/mach/map.h>
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@ -21,6 +22,7 @@
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#define SCU_STANDBY_ENABLE (1 << 5)
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u32 g_diag_reg;
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static void __iomem *scu_base;
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static struct map_desc scu_io_desc __initdata = {
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@ -80,6 +82,18 @@ void imx_smp_prepare(void)
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static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
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{
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imx_smp_prepare();
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/*
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* The diagnostic register holds the errata bits. Mostly bootloader
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* does not bring up secondary cores, so that when errata bits are set
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* in bootloader, they are set only for boot cpu. But on a SMP
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* configuration, it should be equally done on every single core.
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* Read the register from boot cpu here, and will replicate it into
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* secondary cores when booting them.
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*/
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asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
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__cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));
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outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));
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}
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struct smp_operations imx_smp_ops __initdata = {
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