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iommu/arm-smmu: fix calculation of TCR.T0SZ 

T0SZ controls the input address range for TTBR0, so use the input
address range rather than the output address range for the calculation.
For stage-2, this means using the output size of stage-1.

Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2014-06-24 18:26:26 +01:00
parent 7171511eae
commit a65217a4bc
1 changed files with 3 additions and 1 deletions
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4
drivers/iommu/arm-smmu.c
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@ -800,6 +800,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
reg = TTBCR_TG0_64K; reg = TTBCR_TG0_64K;
if (!stage1) { if (!stage1) {
reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
switch (smmu->s2_output_size) { switch (smmu->s2_output_size) {
case 32: case 32:
reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
@ -821,7 +823,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
break; break;
} }
} else { } else {
reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
} }
} else { } else {
reg = 0; reg = 0;