hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omap 

New struct omap_globals contains the omap processor specific
module bases. Use omap_globals to set the various base addresses
to make detecting omap chip type simpler.

Also introduce OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS for future multi-omap
patches.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2008-07-03 12:24:44 +03:00
parent e1f80bfca8
commit a58caad113
11 changed files with 149 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/mach-omap2/cm.h
View File

@ -96,15 +96,10 @@
/* Clock management domain register get/set */
#ifndef __ASSEMBLER__
static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
{
__raw_writel(val, OMAP_CM_REGADDR(module, idx));
}
static inline u32 cm_read_mod_reg(s16 module, s16 idx)
{
return __raw_readl(OMAP_CM_REGADDR(module, idx));
}
extern u32 cm_read_mod_reg(s16 module, u16 idx);
extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
#endif
/* CM register bits shared between 24XX and 3430 */

24
arch/arm/mach-omap2/control.c
View File

@ -13,22 +13,21 @@
#undef DEBUG
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/io.h>
#include <asm/arch/common.h>
#include <asm/arch/control.h>
static u32 omap2_ctrl_base;
static void __iomem *omap2_ctrl_base;
#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
+ (reg))
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
void omap_ctrl_base_set(u32 base)
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
{
omap2_ctrl_base = base;
omap2_ctrl_base = omap2_globals->ctrl;
}
u32 omap_ctrl_base_get(void)
void __iomem *omap_ctrl_base_get(void)
{
return omap2_ctrl_base;
}
@ -50,25 +49,16 @@ u32 omap_ctrl_readl(u16 offset)
void omap_ctrl_writeb(u8 val, u16 offset)
{
pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
(u32)OMAP_CTRL_REGADDR(offset));
__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writew(u16 val, u16 offset)
{
pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
(u32)OMAP_CTRL_REGADDR(offset));
__raw_writew(val, OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writel(u32 val, u16 offset)
{
pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
(u32)OMAP_CTRL_REGADDR(offset));
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}

11
arch/arm/mach-omap2/memory.c
View File

@ -24,6 +24,7 @@
#include <asm/io.h>
#include <asm/arch/common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
@ -32,8 +33,8 @@
#include "memory.h"
#include "sdrc.h"
unsigned long omap2_sdrc_base;
unsigned long omap2_sms_base;
void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;
static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
@ -154,6 +155,12 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
{
omap2_sdrc_base = omap2_globals->sdrc;
omap2_sms_base = omap2_globals->sms;
}
/* turn on smart idle modes for SDRAM scheduler and controller */
void __init omap2_init_memory(void)
{

2
arch/arm/mach-omap2/mux.c
View File

@ -236,7 +236,7 @@ void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
warn = (orig != reg);
if (debug || warn)
printk(KERN_WARNING
"MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
"MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
orig, reg);
}

55
arch/arm/mach-omap2/prcm.c
View File

@ -16,12 +16,18 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/io.h>
#include <asm/arch/common.h>
#include <asm/arch/prcm.h>
#include "clock.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
static void __iomem *prm_base;
static void __iomem *cm_base;
extern void omap2_clk_prepare_for_reboot(void);
u32 omap_prcm_get_reset_sources(void)
@ -41,3 +47,50 @@ void omap_prcm_arch_reset(char mode)
prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
}
}
static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
{
BUG_ON(!base);
return __raw_readl(base + module + reg);
}
static inline void __omap_prcm_write(u32 value, void __iomem *base,
s16 module, u16 reg)
{
BUG_ON(!base);
__raw_writel(value, base + module + reg);
}
/* Read a register in a PRM module */
u32 prm_read_mod_reg(s16 module, u16 idx)
{
return __omap_prcm_read(prm_base, module, idx);
}
EXPORT_SYMBOL(prm_read_mod_reg);
/* Write into a register in a PRM module */
void prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__omap_prcm_write(val, prm_base, module, idx);
}
EXPORT_SYMBOL(prm_write_mod_reg);
/* Read a register in a CM module */
u32 cm_read_mod_reg(s16 module, u16 idx)
{
return __omap_prcm_read(cm_base, module, idx);
}
EXPORT_SYMBOL(cm_read_mod_reg);
/* Write into a register in a CM module */
void cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__omap_prcm_write(val, cm_base, module, idx);
}
EXPORT_SYMBOL(cm_write_mod_reg);
void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
{
prm_base = omap2_globals->prm;
cm_base = omap2_globals->cm;
}

12
arch/arm/mach-omap2/prm.h
View File

@ -166,16 +166,8 @@
#ifndef __ASSEMBLER__
/* Power/reset management domain register get/set */
static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
{
__raw_writel(val, OMAP_PRM_REGADDR(module, idx));
}
static inline u32 prm_read_mod_reg(s16 module, s16 idx)
{
return __raw_readl(OMAP_PRM_REGADDR(module, idx));
}
extern u32 prm_read_mod_reg(s16 module, u16 idx);
extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
#endif

10
arch/arm/mach-omap2/sdrc.h
View File

@ -18,13 +18,11 @@
#include <asm/arch/sdrc.h>
#ifndef __ASSEMBLER__
extern unsigned long omap2_sdrc_base;
extern unsigned long omap2_sms_base;
extern void __iomem *omap2_sdrc_base;
extern void __iomem *omap2_sms_base;
#define OMAP_SDRC_REGADDR(reg) \
(void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
#define OMAP_SMS_REGADDR(reg) \
(void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
#define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
#define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
/* SDRC global register get/set */

59
arch/arm/plat-omap/common.c
View File

@ -26,6 +26,7 @@
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/arch/common.h>
#include <asm/arch/board.h>
#include <asm/arch/control.h>
#include <asm/arch/mux.h>
@ -241,30 +242,70 @@ arch_initcall(omap_init_clocksource_32k);
/* Global address base setup code */
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
static struct omap_globals *omap2_globals;
static void __init __omap2_set_globals(void)
{
omap2_set_globals_memory(omap2_globals);
omap2_set_globals_control(omap2_globals);
omap2_set_globals_prcm(omap2_globals);
}
#endif
#if defined(CONFIG_ARCH_OMAP2420)
static struct omap_globals omap242x_globals = {
.tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
.sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
.sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
.ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
.prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
.cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
};
void __init omap2_set_globals_242x(void)
{
omap2_sdrc_base = OMAP2420_SDRC_BASE;
omap2_sms_base = OMAP2420_SMS_BASE;
omap_ctrl_base_set(OMAP2420_CTRL_BASE);
omap2_globals = &omap242x_globals;
__omap2_set_globals();
}
#endif
#if defined(CONFIG_ARCH_OMAP2430)
static struct omap_globals omap243x_globals = {
.tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
.sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
.sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
.ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
.prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
.cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
};
void __init omap2_set_globals_243x(void)
{
omap2_sdrc_base = OMAP243X_SDRC_BASE;
omap2_sms_base = OMAP243X_SMS_BASE;
omap_ctrl_base_set(OMAP243X_CTRL_BASE);
omap2_globals = &omap243x_globals;
__omap2_set_globals();
}
#endif
#if defined(CONFIG_ARCH_OMAP3430)
static struct omap_globals omap343x_globals = {
.tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
.sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
.sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
.ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
.prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
.cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
};
void __init omap2_set_globals_343x(void)
{
omap2_sdrc_base = OMAP343X_SDRC_BASE;
omap2_sms_base = OMAP343X_SMS_BASE;
omap_ctrl_base_set(OMAP343X_CTRL_BASE);
omap2_globals = &omap343x_globals;
__omap2_set_globals();
}
#endif

15
include/asm-arm/arch-omap/common.h
View File

@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
}
#endif
/* IO bases for various OMAP processors */
struct omap_globals {
void __iomem *tap; /* Control module ID code */
void __iomem *sdrc; /* SDRAM Controller */
void __iomem *sms; /* SDRAM Memory Scheduler */
void __iomem *ctrl; /* System Control Module */
void __iomem *prm; /* Power and Reset Management */
void __iomem *cm; /* Clock Management */
};
void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_343x(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_memory(struct omap_globals *);
void omap2_set_globals_control(struct omap_globals *);
void omap2_set_globals_prcm(struct omap_globals *);
#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

4
include/asm-arm/arch-omap/control.h
View File

@ -167,8 +167,7 @@
#ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
extern void omap_ctrl_base_set(u32 base);
extern u32 omap_ctrl_base_get(void);
extern void __iomem *omap_ctrl_base_get(void);
extern u8 omap_ctrl_readb(u16 offset);
extern u16 omap_ctrl_readw(u16 offset);
extern u32 omap_ctrl_readl(u16 offset);
@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
extern void omap_ctrl_writew(u16 val, u16 offset);
extern void omap_ctrl_writel(u32 val, u16 offset);
#else
#define omap_ctrl_base_set(x) WARN_ON(1)
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
#define omap_ctrl_readw(x) 0

3
include/asm-arm/arch-omap/io.h
View File

@ -60,6 +60,7 @@
#define IO_SIZE 0x40000
#define IO_VIRT (IO_PHYS - IO_OFFSET)
#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
#define io_p2v(pa) ((pa) - IO_OFFSET)
#define io_v2p(va) ((va) + IO_OFFSET)
@ -91,6 +92,7 @@
#define IO_OFFSET 0x90000000
#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
@ -148,6 +150,7 @@
#define IO_OFFSET 0x90000000
#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */