[ARM] 3427/1: ARM: OMAP: 2/8 Update timers
Patch from Tony Lindgren Update OMAP timers from linux-omap tree. The highlights of the patch are: - Move timer32k code from mach-omap1 to plat-omap and make it work also on omap24xx by Tony Lindgren - Add support for dmtimer idle check for PM by Tuukka Tikkanen Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
Russell King
parent
b824efae12
commit
a569c6ec37
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@ -51,8 +51,6 @@
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struct sys_timer omap_timer;
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#ifdef CONFIG_OMAP_MPU_TIMER
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/*
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* ---------------------------------------------------------------------------
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* MPU timer
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@ -222,195 +220,6 @@ unsigned long long sched_clock(void)
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return cycles_2_ns(ticks64);
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}
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#endif /* CONFIG_OMAP_MPU_TIMER */
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#ifdef CONFIG_OMAP_32K_TIMER
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#ifdef CONFIG_ARCH_OMAP15XX
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#error OMAP 32KHz timer does not currently work on 15XX!
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#endif
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/*
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* ---------------------------------------------------------------------------
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* 32KHz OS timer
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*
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* This currently works only on 16xx, as 1510 does not have the continuous
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* 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
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* of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
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* on 1510 would be possible, but the timer would not be as accurate as
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* with the 32KHz synchronized timer.
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* ---------------------------------------------------------------------------
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*/
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#define OMAP_32K_TIMER_BASE 0xfffb9000
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#define OMAP_32K_TIMER_CR 0x08
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#define OMAP_32K_TIMER_TVR 0x00
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#define OMAP_32K_TIMER_TCR 0x04
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#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
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/*
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* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
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* so with HZ = 100, TVR = 327.68.
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*/
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#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
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#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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omap_writew(val, reg + OMAP_32K_TIMER_BASE);
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}
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static inline unsigned long omap_32k_timer_read(int reg)
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{
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return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
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}
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/*
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* The 32KHz synchronized timer is an additional timer on 16xx.
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* It is always running.
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*/
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static inline unsigned long omap_32k_sync_timer_read(void)
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{
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
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}
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/*
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* Rounds down to nearest usec. Note that this will overflow for larger values.
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*/
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static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
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{
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return (ticks_32k * 5*5*5*5*5*5) >> 9;
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}
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/*
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* Rounds down to nearest nsec.
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*/
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static inline unsigned long long
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omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
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{
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return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
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}
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static unsigned long omap_32k_last_tick = 0;
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/*
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* Returns elapsed usecs since last 32k timer interrupt
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*/
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static unsigned long omap_32k_timer_gettimeoffset(void)
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{
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unsigned long now = omap_32k_sync_timer_read();
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return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
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}
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/*
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* Returns current time from boot in nsecs. It's OK for this to wrap
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* around for now, as it's just a relative time stamp.
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*/
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unsigned long long sched_clock(void)
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{
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return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
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}
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/*
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* Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
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* function is also called from other interrupts to remove latency
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* issues with dynamic tick. In the dynamic tick case, we need to lock
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* with irqsave.
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*/
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static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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unsigned long flags;
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unsigned long now;
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write_seqlock_irqsave(&xtime_lock, flags);
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now = omap_32k_sync_timer_read();
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while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
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omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
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timer_tick(regs);
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}
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/* Restart timer so we don't drift off due to modulo or dynamic tick.
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* By default we program the next timer to be continuous to avoid
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* latencies during high system load. During dynamic tick operation the
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* continuous timer can be overridden from pm_idle to be longer.
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*/
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omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
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write_sequnlock_irqrestore(&xtime_lock, flags);
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_NO_IDLE_HZ
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/*
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* Programs the next timer interrupt needed. Called when dynamic tick is
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* enabled, and to reprogram the ticks to skip from pm_idle. Note that
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* we can keep the timer continuous, and don't need to set it to run in
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* one-shot mode. This is because the timer will get reprogrammed again
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* after next interrupt.
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*/
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void omap_32k_timer_reprogram(unsigned long next_tick)
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{
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omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
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}
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static struct irqaction omap_32k_timer_irq;
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extern struct timer_update_handler timer_update;
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static int omap_32k_timer_enable_dyn_tick(void)
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{
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/* No need to reprogram timer, just use the next interrupt */
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return 0;
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}
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static int omap_32k_timer_disable_dyn_tick(void)
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{
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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return 0;
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}
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static struct dyn_tick_timer omap_dyn_tick_timer = {
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.enable = omap_32k_timer_enable_dyn_tick,
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.disable = omap_32k_timer_disable_dyn_tick,
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.reprogram = omap_32k_timer_reprogram,
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.handler = omap_32k_timer_interrupt,
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};
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#endif /* CONFIG_NO_IDLE_HZ */
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static struct irqaction omap_32k_timer_irq = {
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.name = "32KHz timer",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = omap_32k_timer_interrupt,
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};
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static __init void omap_init_32k_timer(void)
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{
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#ifdef CONFIG_NO_IDLE_HZ
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omap_timer.dyn_tick = &omap_dyn_tick_timer;
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#endif
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setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
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omap_timer.offset = omap_32k_timer_gettimeoffset;
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omap_32k_last_tick = omap_32k_sync_timer_read();
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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}
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#endif /* CONFIG_OMAP_32K_TIMER */
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/*
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* ---------------------------------------------------------------------------
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@ -419,13 +228,7 @@ static __init void omap_init_32k_timer(void)
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*/
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static void __init omap_timer_init(void)
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{
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#if defined(CONFIG_OMAP_MPU_TIMER)
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omap_init_mpu_timer();
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#elif defined(CONFIG_OMAP_32K_TIMER)
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omap_init_32k_timer();
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#else
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#error No system timer selected in Kconfig!
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#endif
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}
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struct sys_timer omap_timer = {
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@ -70,13 +70,13 @@ config OMAP_MPU_TIMER
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config OMAP_32K_TIMER
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bool "Use 32KHz timer"
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depends on ARCH_OMAP16XX
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depends on ARCH_OMAP16XX || ARCH_OMAP24XX
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help
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Select this option if you want to enable the OMAP 32KHz timer.
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This timer saves power compared to the OMAP_MPU_TIMER, and has
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support for no tick during idle. The 32KHz timer provides less
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intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
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currently only available for OMAP-16xx.
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currently only available for OMAP16XX and 24XX.
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endchoice
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@ -97,6 +97,32 @@ int omap_dm_timers_active(void)
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}
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/**
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* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
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* @inputmask: current value of idlect mask
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*/
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
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{
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int n;
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/* If ARMXOR cannot be idled this function call is unnecessary */
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if (!(inputmask & (1 << 1)))
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return inputmask;
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/* If any active timer is using ARMXOR return modified mask */
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for (n = 0; dm_timers[n].base; ++n)
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if (omap_dm_timer_read_reg(&dm_timers[n], OMAP_TIMER_CTRL_REG)&
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OMAP_TIMER_CTRL_ST) {
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if (((omap_readl(MOD_CONF_CTRL_1)>>(n*2)) & 0x03) == 0)
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inputmask &= ~(1 << 1);
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else
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inputmask &= ~(1 << 2);
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}
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return inputmask;
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}
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void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
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int n = (timer - dm_timers) << 1;
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@ -0,0 +1,325 @@
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/*
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* linux/arch/arm/plat-omap/timer32k.c
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*
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* OMAP 32K Timer
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*
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* Copyright (C) 2004 - 2005 Nokia Corporation
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* Partial timer rewrite and additional dynamic tick timer support by
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* Tony Lindgen <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* MPU timer code based on the older MPU timer code for OMAP
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/leds.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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struct sys_timer omap_timer;
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/*
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* ---------------------------------------------------------------------------
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* 32KHz OS timer
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*
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* This currently works only on 16xx, as 1510 does not have the continuous
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* 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
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* of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
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* on 1510 would be possible, but the timer would not be as accurate as
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* with the 32KHz synchronized timer.
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* ---------------------------------------------------------------------------
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*/
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#if defined(CONFIG_ARCH_OMAP16XX)
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#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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#elif defined(CONFIG_ARCH_OMAP24XX)
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#define TIMER_32K_SYNCHRONIZED 0x48004010
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#else
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#error OMAP 32KHz timer does not currently work on 15XX!
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#endif
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/* 16xx specific defines */
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#define OMAP1_32K_TIMER_BASE 0xfffb9000
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#define OMAP1_32K_TIMER_CR 0x08
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#define OMAP1_32K_TIMER_TVR 0x00
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#define OMAP1_32K_TIMER_TCR 0x04
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/* 24xx specific defines */
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#define OMAP2_GP_TIMER_BASE 0x48028000
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#define CM_CLKSEL_WKUP 0x48008440
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#define GP_TIMER_TIDR 0x00
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#define GP_TIMER_TISR 0x18
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#define GP_TIMER_TIER 0x1c
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#define GP_TIMER_TCLR 0x24
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#define GP_TIMER_TCRR 0x28
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#define GP_TIMER_TLDR 0x2c
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#define GP_TIMER_TTGR 0x30
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#define GP_TIMER_TSICR 0x40
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#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
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/*
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* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
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* so with HZ = 128, TVR = 255.
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*/
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#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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if (cpu_class_is_omap1())
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omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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if (cpu_is_omap24xx())
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omap_writel(val, OMAP2_GP_TIMER_BASE + reg);
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}
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static inline unsigned long omap_32k_timer_read(int reg)
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{
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if (cpu_class_is_omap1())
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return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
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if (cpu_is_omap24xx())
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return omap_readl(OMAP2_GP_TIMER_BASE + reg);
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}
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/*
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* The 32KHz synchronized timer is an additional timer on 16xx.
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* It is always running.
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*/
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static inline unsigned long omap_32k_sync_timer_read(void)
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{
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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if (cpu_class_is_omap1()) {
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omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
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}
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if (cpu_is_omap24xx()) {
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omap_32k_timer_write(0xffffffff - load_val, GP_TIMER_TCRR);
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omap_32k_timer_write((1 << 1), GP_TIMER_TIER);
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omap_32k_timer_write((1 << 1) | 1, GP_TIMER_TCLR);
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}
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}
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static inline void omap_32k_timer_stop(void)
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{
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if (cpu_class_is_omap1())
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omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
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if (cpu_is_omap24xx())
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omap_32k_timer_write(0x0, GP_TIMER_TCLR);
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}
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/*
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* Rounds down to nearest usec. Note that this will overflow for larger values.
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*/
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static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
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{
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return (ticks_32k * 5*5*5*5*5*5) >> 9;
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}
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/*
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* Rounds down to nearest nsec.
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*/
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static inline unsigned long long
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omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
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{
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return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
|
||||
}
|
||||
|
||||
static unsigned long omap_32k_last_tick = 0;
|
||||
|
||||
/*
|
||||
* Returns elapsed usecs since last 32k timer interrupt
|
||||
*/
|
||||
static unsigned long omap_32k_timer_gettimeoffset(void)
|
||||
{
|
||||
unsigned long now = omap_32k_sync_timer_read();
|
||||
return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns current time from boot in nsecs. It's OK for this to wrap
|
||||
* around for now, as it's just a relative time stamp.
|
||||
*/
|
||||
unsigned long long sched_clock(void)
|
||||
{
|
||||
return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
|
||||
}
|
||||
|
||||
/*
|
||||
* Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
|
||||
* function is also called from other interrupts to remove latency
|
||||
* issues with dynamic tick. In the dynamic tick case, we need to lock
|
||||
* with irqsave.
|
||||
*/
|
||||
static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long now;
|
||||
|
||||
write_seqlock_irqsave(&xtime_lock, flags);
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
u32 status = omap_32k_timer_read(GP_TIMER_TISR);
|
||||
omap_32k_timer_write(status, GP_TIMER_TISR);
|
||||
}
|
||||
|
||||
now = omap_32k_sync_timer_read();
|
||||
|
||||
while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
|
||||
omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
|
||||
timer_tick(regs);
|
||||
}
|
||||
|
||||
/* Restart timer so we don't drift off due to modulo or dynamic tick.
|
||||
* By default we program the next timer to be continuous to avoid
|
||||
* latencies during high system load. During dynamic tick operation the
|
||||
* continuous timer can be overridden from pm_idle to be longer.
|
||||
*/
|
||||
omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
|
||||
write_sequnlock_irqrestore(&xtime_lock, flags);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
/*
|
||||
* Programs the next timer interrupt needed. Called when dynamic tick is
|
||||
* enabled, and to reprogram the ticks to skip from pm_idle. Note that
|
||||
* we can keep the timer continuous, and don't need to set it to run in
|
||||
* one-shot mode. This is because the timer will get reprogrammed again
|
||||
* after next interrupt.
|
||||
*/
|
||||
void omap_32k_timer_reprogram(unsigned long next_tick)
|
||||
{
|
||||
omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
|
||||
}
|
||||
|
||||
static struct irqaction omap_32k_timer_irq;
|
||||
extern struct timer_update_handler timer_update;
|
||||
|
||||
static int omap_32k_timer_enable_dyn_tick(void)
|
||||
{
|
||||
/* No need to reprogram timer, just use the next interrupt */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_32k_timer_disable_dyn_tick(void)
|
||||
{
|
||||
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dyn_tick_timer omap_dyn_tick_timer = {
|
||||
.enable = omap_32k_timer_enable_dyn_tick,
|
||||
.disable = omap_32k_timer_disable_dyn_tick,
|
||||
.reprogram = omap_32k_timer_reprogram,
|
||||
.handler = omap_32k_timer_interrupt,
|
||||
};
|
||||
#endif /* CONFIG_NO_IDLE_HZ */
|
||||
|
||||
static struct irqaction omap_32k_timer_irq = {
|
||||
.name = "32KHz timer",
|
||||
.flags = SA_INTERRUPT | SA_TIMER,
|
||||
.handler = omap_32k_timer_interrupt,
|
||||
};
|
||||
|
||||
static struct clk * gpt1_ick;
|
||||
static struct clk * gpt1_fck;
|
||||
|
||||
static __init void omap_init_32k_timer(void)
|
||||
{
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
omap_timer.dyn_tick = &omap_dyn_tick_timer;
|
||||
#endif
|
||||
|
||||
if (cpu_class_is_omap1())
|
||||
setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
|
||||
if (cpu_is_omap24xx())
|
||||
setup_irq(37, &omap_32k_timer_irq);
|
||||
omap_timer.offset = omap_32k_timer_gettimeoffset;
|
||||
omap_32k_last_tick = omap_32k_sync_timer_read();
|
||||
|
||||
/* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
|
||||
if (cpu_is_omap24xx()) {
|
||||
omap_32k_timer_write(0, GP_TIMER_TCLR);
|
||||
omap_writel(0, CM_CLKSEL_WKUP); /* 32KHz clock source */
|
||||
|
||||
gpt1_ick = clk_get(NULL, "gpt1_ick");
|
||||
if (IS_ERR(gpt1_ick))
|
||||
printk(KERN_ERR "Could not get gpt1_ick\n");
|
||||
else
|
||||
clk_enable(gpt1_ick);
|
||||
|
||||
gpt1_fck = clk_get(NULL, "gpt1_fck");
|
||||
if (IS_ERR(gpt1_fck))
|
||||
printk(KERN_ERR "Could not get gpt1_fck\n");
|
||||
else
|
||||
clk_enable(gpt1_fck);
|
||||
|
||||
mdelay(100); /* Wait for clocks to stabilize */
|
||||
|
||||
omap_32k_timer_write(0x7, GP_TIMER_TISR);
|
||||
}
|
||||
|
||||
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
|
||||
}
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* Timer initialization
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
static void __init omap_timer_init(void)
|
||||
{
|
||||
omap_init_32k_timer();
|
||||
}
|
||||
|
||||
struct sys_timer omap_timer = {
|
||||
.init = omap_timer_init,
|
||||
.offset = NULL, /* Initialized later */
|
||||
};
|
||||
|
|
@ -88,5 +88,6 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
|
|||
void omap_dm_timer_reset_counter(struct omap_dm_timer *timer);
|
||||
|
||||
int omap_dm_timers_active(void);
|
||||
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
|
||||
|
||||
#endif /* __ASM_ARCH_TIMER_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-omap/param.h
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_OMAP_32K_TIMER_HZ
|
||||
#define HZ CONFIG_OMAP_32K_TIMER_HZ
|
||||
#endif
|
||||
Loading…
Reference in New Issue