Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org/git/drm-intel into i2c/for-next
Pull immutable branch as a common base for further development: "Baytrail PMIC vs. PMU race fixes from Hans de Goede This time the right version (v4), with the compile fix."
This commit is contained in:
Wolfram Sang
commit
a528fab6cc
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@ -5,6 +5,8 @@
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#ifndef IOSF_MBI_SYMS_H
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#define IOSF_MBI_SYMS_H
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#include <linux/notifier.h>
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#define MBI_MCR_OFFSET 0xD0
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#define MBI_MDR_OFFSET 0xD4
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#define MBI_MCRX_OFFSET 0xD8
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@ -47,6 +49,10 @@
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#define QRK_MBI_UNIT_MM 0x05
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#define QRK_MBI_UNIT_SOC 0x31
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/* Action values for the pmic_bus_access_notifier functions */
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#define MBI_PMIC_BUS_ACCESS_BEGIN 1
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#define MBI_PMIC_BUS_ACCESS_END 2
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#if IS_ENABLED(CONFIG_IOSF_MBI)
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bool iosf_mbi_available(void);
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@ -88,6 +94,65 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
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*/
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
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/**
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* iosf_mbi_punit_acquire() - Acquire access to the P-Unit
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*
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* One some systems the P-Unit accesses the PMIC to change various voltages
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* through the same bus as other kernel drivers use for e.g. battery monitoring.
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*
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* If a driver sends requests to the P-Unit which require the P-Unit to access
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* the PMIC bus while another driver is also accessing the PMIC bus various bad
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* things happen.
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*
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* To avoid these problems this function must be called before accessing the
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* P-Unit or the PMIC, be it through iosf_mbi* functions or through other means.
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*
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* Note on these systems the i2c-bus driver will request a sempahore from the
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* P-Unit for exclusive access to the PMIC bus when i2c drivers are accessing
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* it, but this does not appear to be sufficient, we still need to avoid making
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* certain P-Unit requests during the access window to avoid problems.
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*
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* This function locks a mutex, as such it may sleep.
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*/
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void iosf_mbi_punit_acquire(void);
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/**
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* iosf_mbi_punit_release() - Release access to the P-Unit
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*/
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void iosf_mbi_punit_release(void);
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/**
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* iosf_mbi_register_pmic_bus_access_notifier - Register PMIC bus notifier
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*
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* This function can be used by drivers which may need to acquire P-Unit
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* managed resources from interrupt context, where iosf_mbi_punit_acquire()
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* can not be used.
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*
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* This function allows a driver to register a notifier to get notified (in a
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* process context) before other drivers start accessing the PMIC bus.
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*
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* This allows the driver to acquire any resources, which it may need during
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* the window the other driver is accessing the PMIC, before hand.
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*
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* @nb: notifier_block to register
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*/
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int iosf_mbi_register_pmic_bus_access_notifier(struct notifier_block *nb);
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/**
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* iosf_mbi_register_pmic_bus_access_notifier - Unregister PMIC bus notifier
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*
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* @nb: notifier_block to unregister
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*/
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int iosf_mbi_unregister_pmic_bus_access_notifier(struct notifier_block *nb);
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/**
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* iosf_mbi_call_pmic_bus_access_notifier_chain - Call PMIC bus notifier chain
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*
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* @val: action to pass into listener's notifier_call function
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* @v: data pointer to pass into listener's notifier_call function
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*/
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int iosf_mbi_call_pmic_bus_access_notifier_chain(unsigned long val, void *v);
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#else /* CONFIG_IOSF_MBI is not enabled */
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static inline
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bool iosf_mbi_available(void)
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@ -115,6 +180,28 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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static inline void iosf_mbi_punit_acquire(void) {}
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static inline void iosf_mbi_punit_release(void) {}
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static inline
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int iosf_mbi_register_pmic_bus_access_notifier(struct notifier_block *nb)
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{
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return 0;
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}
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static inline
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int iosf_mbi_unregister_pmic_bus_access_notifier(struct notifier_block *nb)
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{
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return 0;
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}
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static inline
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int iosf_mbi_call_pmic_bus_access_notifier_chain(unsigned long val, void *v)
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{
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return 0;
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}
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#endif /* CONFIG_IOSF_MBI */
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#endif /* IOSF_MBI_SYMS_H */
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@ -34,6 +34,8 @@
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static struct pci_dev *mbi_pdev;
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static DEFINE_SPINLOCK(iosf_mbi_lock);
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static DEFINE_MUTEX(iosf_mbi_punit_mutex);
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static BLOCKING_NOTIFIER_HEAD(iosf_mbi_pmic_bus_access_notifier);
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static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
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{
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@ -190,6 +192,53 @@ bool iosf_mbi_available(void)
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}
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EXPORT_SYMBOL(iosf_mbi_available);
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void iosf_mbi_punit_acquire(void)
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{
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mutex_lock(&iosf_mbi_punit_mutex);
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}
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EXPORT_SYMBOL(iosf_mbi_punit_acquire);
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void iosf_mbi_punit_release(void)
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{
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mutex_unlock(&iosf_mbi_punit_mutex);
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}
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EXPORT_SYMBOL(iosf_mbi_punit_release);
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int iosf_mbi_register_pmic_bus_access_notifier(struct notifier_block *nb)
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{
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int ret;
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/* Wait for the bus to go inactive before registering */
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mutex_lock(&iosf_mbi_punit_mutex);
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ret = blocking_notifier_chain_register(
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&iosf_mbi_pmic_bus_access_notifier, nb);
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mutex_unlock(&iosf_mbi_punit_mutex);
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return ret;
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}
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EXPORT_SYMBOL(iosf_mbi_register_pmic_bus_access_notifier);
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int iosf_mbi_unregister_pmic_bus_access_notifier(struct notifier_block *nb)
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{
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int ret;
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/* Wait for the bus to go inactive before unregistering */
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mutex_lock(&iosf_mbi_punit_mutex);
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ret = blocking_notifier_chain_unregister(
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&iosf_mbi_pmic_bus_access_notifier, nb);
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mutex_unlock(&iosf_mbi_punit_mutex);
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return ret;
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}
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EXPORT_SYMBOL(iosf_mbi_unregister_pmic_bus_access_notifier);
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int iosf_mbi_call_pmic_bus_access_notifier_chain(unsigned long val, void *v)
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{
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return blocking_notifier_call_chain(
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&iosf_mbi_pmic_bus_access_notifier, val, v);
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}
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EXPORT_SYMBOL(iosf_mbi_call_pmic_bus_access_notifier_chain);
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#ifdef CONFIG_IOSF_MBI_DEBUG
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static u32 dbg_mdr;
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static u32 dbg_mcr;
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@ -19,6 +19,7 @@ config DRM_I915
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select INPUT if ACPI
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select ACPI_VIDEO if ACPI
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select ACPI_BUTTON if ACPI
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select IOSF_MBI
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help
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Choose this option if you have a system that has "Intel Graphics
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Media Accelerator" or "HD Graphics" integrated graphics,
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|
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@ -1456,7 +1456,7 @@ static int i915_drm_suspend(struct drm_device *dev)
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opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
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intel_opregion_notify_adapter(dev_priv, opregion_target_state);
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intel_uncore_forcewake_reset(dev_priv, false);
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intel_uncore_suspend(dev_priv);
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intel_opregion_unregister(dev_priv);
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intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
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@ -1701,7 +1701,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
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DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
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ret);
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intel_uncore_early_sanitize(dev_priv, true);
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intel_uncore_resume_early(dev_priv);
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if (IS_GEN9_LP(dev_priv)) {
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if (!dev_priv->suspended_to_idle)
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@ -2343,7 +2343,7 @@ static int intel_runtime_suspend(struct device *kdev)
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return ret;
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}
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intel_uncore_forcewake_reset(dev_priv, false);
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intel_uncore_suspend(dev_priv);
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enable_rpm_wakeref_asserts(dev_priv);
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WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
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@ -723,6 +723,7 @@ struct intel_uncore {
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const struct intel_forcewake_range *fw_domains_table;
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unsigned int fw_domains_table_entries;
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struct notifier_block pmic_bus_access_nb;
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struct intel_uncore_funcs funcs;
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unsigned fifo_count;
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@ -2991,14 +2992,12 @@ int intel_irq_install(struct drm_i915_private *dev_priv);
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void intel_irq_uninstall(struct drm_i915_private *dev_priv);
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extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
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extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
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bool restore_forcewake);
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extern void intel_uncore_init(struct drm_i915_private *dev_priv);
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extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
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extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
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extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
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extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
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bool restore);
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extern void intel_uncore_suspend(struct drm_i915_private *dev_priv);
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extern void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
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const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
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void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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|
|
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@ -25,6 +25,7 @@
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#include "intel_drv.h"
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#include "i915_vgpu.h"
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#include <asm/iosf_mbi.h>
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#include <linux/pm_runtime.h>
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#define FORCEWAKE_ACK_TIMEOUT_MS 50
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@ -252,8 +253,8 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
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return HRTIMER_NORESTART;
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}
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|
||||
void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
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bool restore)
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static void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
|
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bool restore)
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{
|
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unsigned long irqflags;
|
||||
struct intel_uncore_forcewake_domain *domain;
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|
|
@ -429,10 +430,18 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
|
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intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
|
||||
}
|
||||
|
||||
void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
|
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bool restore_forcewake)
|
||||
void intel_uncore_suspend(struct drm_i915_private *dev_priv)
|
||||
{
|
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__intel_uncore_early_sanitize(dev_priv, restore_forcewake);
|
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iosf_mbi_unregister_pmic_bus_access_notifier(
|
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&dev_priv->uncore.pmic_bus_access_nb);
|
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intel_uncore_forcewake_reset(dev_priv, false);
|
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}
|
||||
|
||||
void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
__intel_uncore_early_sanitize(dev_priv, true);
|
||||
iosf_mbi_register_pmic_bus_access_notifier(
|
||||
&dev_priv->uncore.pmic_bus_access_nb);
|
||||
i915_check_and_clear_faults(dev_priv);
|
||||
}
|
||||
|
||||
|
|
@ -1385,6 +1394,32 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
|
|||
dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
|
||||
}
|
||||
|
||||
static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
|
||||
unsigned long action, void *data)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = container_of(nb,
|
||||
struct drm_i915_private, uncore.pmic_bus_access_nb);
|
||||
|
||||
switch (action) {
|
||||
case MBI_PMIC_BUS_ACCESS_BEGIN:
|
||||
/*
|
||||
* forcewake all now to make sure that we don't need to do a
|
||||
* forcewake later which on systems where this notifier gets
|
||||
* called requires the punit to access to the shared pmic i2c
|
||||
* bus, which will be busy after this notification, leading to:
|
||||
* "render: timed out waiting for forcewake ack request."
|
||||
* errors.
|
||||
*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
break;
|
||||
case MBI_PMIC_BUS_ACCESS_END:
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
break;
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
void intel_uncore_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
i915_check_vgpu(dev_priv);
|
||||
|
|
@ -1394,6 +1429,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
|
|||
__intel_uncore_early_sanitize(dev_priv, false);
|
||||
|
||||
dev_priv->uncore.unclaimed_mmio_check = 1;
|
||||
dev_priv->uncore.pmic_bus_access_nb.notifier_call =
|
||||
i915_pmic_bus_access_notifier;
|
||||
|
||||
switch (INTEL_INFO(dev_priv)->gen) {
|
||||
default:
|
||||
|
|
@ -1453,6 +1490,9 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
|
|||
ASSIGN_READ_MMIO_VFUNCS(vgpu);
|
||||
}
|
||||
|
||||
iosf_mbi_register_pmic_bus_access_notifier(
|
||||
&dev_priv->uncore.pmic_bus_access_nb);
|
||||
|
||||
i915_check_and_clear_faults(dev_priv);
|
||||
}
|
||||
#undef ASSIGN_WRITE_MMIO_VFUNCS
|
||||
|
|
@ -1460,6 +1500,9 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
|
|||
|
||||
void intel_uncore_fini(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
iosf_mbi_unregister_pmic_bus_access_notifier(
|
||||
&dev_priv->uncore.pmic_bus_access_nb);
|
||||
|
||||
/* Paranoia: make sure we have disabled everything before we exit. */
|
||||
intel_uncore_sanitize(dev_priv);
|
||||
intel_uncore_forcewake_reset(dev_priv, false);
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/acpi.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pm_qos.h>
|
||||
|
||||
#include <asm/iosf_mbi.h>
|
||||
|
||||
|
|
@ -23,19 +24,29 @@
|
|||
|
||||
#define SEMAPHORE_TIMEOUT 100
|
||||
#define PUNIT_SEMAPHORE 0x7
|
||||
#define PUNIT_SEMAPHORE_CHT 0x10e
|
||||
#define PUNIT_SEMAPHORE_BIT BIT(0)
|
||||
#define PUNIT_SEMAPHORE_ACQUIRE BIT(1)
|
||||
|
||||
static unsigned long acquired;
|
||||
|
||||
static int get_sem(struct device *dev, u32 *sem)
|
||||
static u32 get_sem_addr(struct dw_i2c_dev *dev)
|
||||
{
|
||||
if (dev->flags & MODEL_CHERRYTRAIL)
|
||||
return PUNIT_SEMAPHORE_CHT;
|
||||
else
|
||||
return PUNIT_SEMAPHORE;
|
||||
}
|
||||
|
||||
static int get_sem(struct dw_i2c_dev *dev, u32 *sem)
|
||||
{
|
||||
u32 addr = get_sem_addr(dev);
|
||||
u32 data;
|
||||
int ret;
|
||||
|
||||
ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, PUNIT_SEMAPHORE, &data);
|
||||
ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, addr, &data);
|
||||
if (ret) {
|
||||
dev_err(dev, "iosf failed to read punit semaphore\n");
|
||||
dev_err(dev->dev, "iosf failed to read punit semaphore\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -44,22 +55,22 @@ static int get_sem(struct device *dev, u32 *sem)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void reset_semaphore(struct device *dev)
|
||||
static void reset_semaphore(struct dw_i2c_dev *dev)
|
||||
{
|
||||
u32 data;
|
||||
if (iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, get_sem_addr(dev),
|
||||
0, PUNIT_SEMAPHORE_BIT))
|
||||
dev_err(dev->dev, "iosf failed to reset punit semaphore during write\n");
|
||||
|
||||
if (iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, PUNIT_SEMAPHORE, &data)) {
|
||||
dev_err(dev, "iosf failed to reset punit semaphore during read\n");
|
||||
return;
|
||||
}
|
||||
pm_qos_update_request(&dev->pm_qos, PM_QOS_DEFAULT_VALUE);
|
||||
|
||||
data &= ~PUNIT_SEMAPHORE_BIT;
|
||||
if (iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, PUNIT_SEMAPHORE, data))
|
||||
dev_err(dev, "iosf failed to reset punit semaphore during write\n");
|
||||
iosf_mbi_call_pmic_bus_access_notifier_chain(MBI_PMIC_BUS_ACCESS_END,
|
||||
NULL);
|
||||
iosf_mbi_punit_release();
|
||||
}
|
||||
|
||||
static int baytrail_i2c_acquire(struct dw_i2c_dev *dev)
|
||||
{
|
||||
u32 addr = get_sem_addr(dev);
|
||||
u32 sem = PUNIT_SEMAPHORE_ACQUIRE;
|
||||
int ret;
|
||||
unsigned long start, end;
|
||||
|
|
@ -72,18 +83,29 @@ static int baytrail_i2c_acquire(struct dw_i2c_dev *dev)
|
|||
if (!dev->release_lock)
|
||||
return 0;
|
||||
|
||||
iosf_mbi_punit_acquire();
|
||||
iosf_mbi_call_pmic_bus_access_notifier_chain(MBI_PMIC_BUS_ACCESS_BEGIN,
|
||||
NULL);
|
||||
|
||||
/*
|
||||
* Disallow the CPU to enter C6 or C7 state, entering these states
|
||||
* requires the punit to talk to the pmic and if this happens while
|
||||
* we're holding the semaphore, the SoC hangs.
|
||||
*/
|
||||
pm_qos_update_request(&dev->pm_qos, 0);
|
||||
|
||||
/* host driver writes to side band semaphore register */
|
||||
ret = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, PUNIT_SEMAPHORE, sem);
|
||||
ret = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, addr, sem);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "iosf punit semaphore request failed\n");
|
||||
return ret;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* host driver waits for bit 0 to be set in semaphore register */
|
||||
start = jiffies;
|
||||
end = start + msecs_to_jiffies(SEMAPHORE_TIMEOUT);
|
||||
do {
|
||||
ret = get_sem(dev->dev, &sem);
|
||||
ret = get_sem(dev, &sem);
|
||||
if (!ret && sem) {
|
||||
acquired = jiffies;
|
||||
dev_dbg(dev->dev, "punit semaphore acquired after %ums\n",
|
||||
|
|
@ -95,9 +117,10 @@ static int baytrail_i2c_acquire(struct dw_i2c_dev *dev)
|
|||
} while (time_before(jiffies, end));
|
||||
|
||||
dev_err(dev->dev, "punit semaphore timed out, resetting\n");
|
||||
reset_semaphore(dev->dev);
|
||||
out:
|
||||
reset_semaphore(dev);
|
||||
|
||||
ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, PUNIT_SEMAPHORE, &sem);
|
||||
ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, addr, &sem);
|
||||
if (ret)
|
||||
dev_err(dev->dev, "iosf failed to read punit semaphore\n");
|
||||
else
|
||||
|
|
@ -116,12 +139,12 @@ static void baytrail_i2c_release(struct dw_i2c_dev *dev)
|
|||
if (!dev->acquire_lock)
|
||||
return;
|
||||
|
||||
reset_semaphore(dev->dev);
|
||||
reset_semaphore(dev);
|
||||
dev_dbg(dev->dev, "punit semaphore held for %ums\n",
|
||||
jiffies_to_msecs(jiffies - acquired));
|
||||
}
|
||||
|
||||
int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev)
|
||||
int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev)
|
||||
{
|
||||
acpi_status status;
|
||||
unsigned long long shared_host = 0;
|
||||
|
|
@ -138,15 +161,25 @@ int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev)
|
|||
if (ACPI_FAILURE(status))
|
||||
return 0;
|
||||
|
||||
if (shared_host) {
|
||||
dev_info(dev->dev, "I2C bus managed by PUNIT\n");
|
||||
dev->acquire_lock = baytrail_i2c_acquire;
|
||||
dev->release_lock = baytrail_i2c_release;
|
||||
dev->pm_runtime_disabled = true;
|
||||
}
|
||||
if (!shared_host)
|
||||
return 0;
|
||||
|
||||
if (!iosf_mbi_available())
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_info(dev->dev, "I2C bus managed by PUNIT\n");
|
||||
dev->acquire_lock = baytrail_i2c_acquire;
|
||||
dev->release_lock = baytrail_i2c_release;
|
||||
dev->pm_runtime_disabled = true;
|
||||
|
||||
pm_qos_add_request(&dev->pm_qos, PM_QOS_CPU_DMA_LATENCY,
|
||||
PM_QOS_DEFAULT_VALUE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev)
|
||||
{
|
||||
if (dev->acquire_lock)
|
||||
pm_qos_remove_request(&dev->pm_qos);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -177,13 +177,13 @@ static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
|
|||
{
|
||||
u32 value;
|
||||
|
||||
if (dev->accessor_flags & ACCESS_16BIT)
|
||||
if (dev->flags & ACCESS_16BIT)
|
||||
value = readw_relaxed(dev->base + offset) |
|
||||
(readw_relaxed(dev->base + offset + 2) << 16);
|
||||
else
|
||||
value = readl_relaxed(dev->base + offset);
|
||||
|
||||
if (dev->accessor_flags & ACCESS_SWAP)
|
||||
if (dev->flags & ACCESS_SWAP)
|
||||
return swab32(value);
|
||||
else
|
||||
return value;
|
||||
|
|
@ -191,10 +191,10 @@ static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
|
|||
|
||||
static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
|
||||
{
|
||||
if (dev->accessor_flags & ACCESS_SWAP)
|
||||
if (dev->flags & ACCESS_SWAP)
|
||||
b = swab32(b);
|
||||
|
||||
if (dev->accessor_flags & ACCESS_16BIT) {
|
||||
if (dev->flags & ACCESS_16BIT) {
|
||||
writew_relaxed((u16)b, dev->base + offset);
|
||||
writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
|
||||
} else {
|
||||
|
|
@ -339,10 +339,10 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
|
|||
reg = dw_readl(dev, DW_IC_COMP_TYPE);
|
||||
if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
|
||||
/* Configure register endianess access */
|
||||
dev->accessor_flags |= ACCESS_SWAP;
|
||||
dev->flags |= ACCESS_SWAP;
|
||||
} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
|
||||
/* Configure register access mode 16bit */
|
||||
dev->accessor_flags |= ACCESS_16BIT;
|
||||
dev->flags |= ACCESS_16BIT;
|
||||
} else if (reg != DW_IC_COMP_TYPE_VALUE) {
|
||||
dev_err(dev->dev, "Unknown Synopsys component type: "
|
||||
"0x%08x\n", reg);
|
||||
|
|
@ -924,7 +924,7 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
|||
tx_aborted:
|
||||
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
|
||||
complete(&dev->cmd_complete);
|
||||
else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
|
||||
else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
|
||||
/* workaround to trigger pending interrupt */
|
||||
stat = dw_readl(dev, DW_IC_INTR_MASK);
|
||||
i2c_dw_disable_int(dev);
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/pm_qos.h>
|
||||
|
||||
#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
|
||||
I2C_FUNC_SMBUS_BYTE | \
|
||||
|
|
@ -75,6 +76,7 @@
|
|||
* @fp_lcnt: fast plus LCNT value
|
||||
* @hs_hcnt: high speed HCNT value
|
||||
* @hs_lcnt: high speed LCNT value
|
||||
* @pm_qos: pm_qos_request used while holding a hardware lock on the bus
|
||||
* @acquire_lock: function to acquire a hardware lock on the bus
|
||||
* @release_lock: function to release a hardware lock on the bus
|
||||
* @pm_runtime_disabled: true if pm runtime is disabled
|
||||
|
|
@ -104,7 +106,7 @@ struct dw_i2c_dev {
|
|||
unsigned int status;
|
||||
u32 abort_source;
|
||||
int irq;
|
||||
u32 accessor_flags;
|
||||
u32 flags;
|
||||
struct i2c_adapter adapter;
|
||||
u32 functionality;
|
||||
u32 master_cfg;
|
||||
|
|
@ -123,6 +125,7 @@ struct dw_i2c_dev {
|
|||
u16 fp_lcnt;
|
||||
u16 hs_hcnt;
|
||||
u16 hs_lcnt;
|
||||
struct pm_qos_request pm_qos;
|
||||
int (*acquire_lock)(struct dw_i2c_dev *dev);
|
||||
void (*release_lock)(struct dw_i2c_dev *dev);
|
||||
bool pm_runtime_disabled;
|
||||
|
|
@ -132,6 +135,8 @@ struct dw_i2c_dev {
|
|||
#define ACCESS_16BIT 0x00000002
|
||||
#define ACCESS_INTR_MASK 0x00000004
|
||||
|
||||
#define MODEL_CHERRYTRAIL 0x00000100
|
||||
|
||||
extern int i2c_dw_init(struct dw_i2c_dev *dev);
|
||||
extern void i2c_dw_disable(struct dw_i2c_dev *dev);
|
||||
extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
|
||||
|
|
@ -139,7 +144,9 @@ extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
|
|||
extern int i2c_dw_probe(struct dw_i2c_dev *dev);
|
||||
|
||||
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
|
||||
extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
|
||||
extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev);
|
||||
extern void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev);
|
||||
#else
|
||||
static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }
|
||||
static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; }
|
||||
static inline void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev) {}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ enum dw_pci_ctl_id_t {
|
|||
medfield,
|
||||
merrifield,
|
||||
baytrail,
|
||||
cherrytrail,
|
||||
haswell,
|
||||
};
|
||||
|
||||
|
|
@ -63,6 +64,7 @@ struct dw_pci_controller {
|
|||
u32 rx_fifo_depth;
|
||||
u32 clk_khz;
|
||||
u32 functionality;
|
||||
u32 flags;
|
||||
struct dw_scl_sda_cfg *scl_sda_cfg;
|
||||
int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
|
||||
};
|
||||
|
|
@ -170,6 +172,15 @@ static struct dw_pci_controller dw_pci_controllers[] = {
|
|||
.functionality = I2C_FUNC_10BIT_ADDR,
|
||||
.scl_sda_cfg = &hsw_config,
|
||||
},
|
||||
[cherrytrail] = {
|
||||
.bus_num = -1,
|
||||
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
|
||||
.tx_fifo_depth = 32,
|
||||
.rx_fifo_depth = 32,
|
||||
.functionality = I2C_FUNC_10BIT_ADDR,
|
||||
.flags = MODEL_CHERRYTRAIL,
|
||||
.scl_sda_cfg = &byt_config,
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -237,6 +248,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
|
|||
dev->base = pcim_iomap_table(pdev)[0];
|
||||
dev->dev = &pdev->dev;
|
||||
dev->irq = pdev->irq;
|
||||
dev->flags |= controller->flags;
|
||||
|
||||
if (controller->setup) {
|
||||
r = controller->setup(pdev, controller);
|
||||
|
|
@ -317,13 +329,13 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
|
|||
{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
|
||||
{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
|
||||
/* Braswell / Cherrytrail */
|
||||
{ PCI_VDEVICE(INTEL, 0x22C1), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C2), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C3), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C4), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C5), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C6), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C7), baytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
|
||||
{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
|
||||
{ 0,}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ static int dw_i2c_acpi_configure(struct platform_device *pdev)
|
|||
|
||||
id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev);
|
||||
if (id && id->driver_data)
|
||||
dev->accessor_flags |= (u32)id->driver_data;
|
||||
dev->flags |= (u32)id->driver_data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -124,7 +124,7 @@ static const struct acpi_device_id dw_i2c_acpi_match[] = {
|
|||
{ "INT3432", 0 },
|
||||
{ "INT3433", 0 },
|
||||
{ "80860F41", 0 },
|
||||
{ "808622C1", 0 },
|
||||
{ "808622C1", MODEL_CHERRYTRAIL },
|
||||
{ "AMD0010", ACCESS_INTR_MASK },
|
||||
{ "AMDI0010", ACCESS_INTR_MASK },
|
||||
{ "AMDI0510", 0 },
|
||||
|
|
@ -248,7 +248,7 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
|
|||
goto exit_reset;
|
||||
}
|
||||
|
||||
r = i2c_dw_eval_lock_support(dev);
|
||||
r = i2c_dw_probe_lock_support(dev);
|
||||
if (r)
|
||||
goto exit_reset;
|
||||
|
||||
|
|
@ -327,6 +327,8 @@ static int dw_i2c_plat_remove(struct platform_device *pdev)
|
|||
if (!IS_ERR_OR_NULL(dev->rst))
|
||||
reset_control_assert(dev->rst);
|
||||
|
||||
i2c_dw_remove_lock_support(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue