2nd Amlogic clock driver update for 4.12:
* Protect against holes in onecell_data * Fix divison by zero and overflow in the mpll driver * Add audio clock divider driver for i2s clocks * Add i2s and spdif master clocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJY57jYAAoJEAFRo5MEFpTRgEUQALTIayOZGZHQu+xFe0UMHCkO HX+jSNn/CLbf+pOexZash/jGEckdWU7jLsrjRottld+duWAt15rT5hI7ZBe9e2kG uknLGKWpznuxq0BgF7d1rbm2+cjrQG5GKa3yYUKxW1jr62iQRDA2WH2LfJElvNC7 hFELnzF/kaqP+ErWZyEI6TWknUrajpx30XewqknyQ2xDJawoh+YqhEBRLbc8Slh8 JLwU4m7VyK0Wt988LyAbQH9VvvejwrgMZvleVy24z+hKnjgxTlefy6dioKNMchNH e6FIJ/yDz6YhJaK2a6Kd3ZmouQRXkH8jodVWOfIfQQSDDpuzdHSHJGHh2rwDRvwz hM2y4Yd05svpMzl9YxqZFhsqHZSZegZhhR+rdhv7u5I96DVY9xPQC2QGK2hroLRU 0pZU7XKL6rlG9lSqGCIGLzD/gIuwBco385MJUzdkRL7AHf79sXuPeyPYHxD2ox/8 u+g1ek7bex/5xkd4/n6umoqbSsURzObu4FH2EUn5fIR9Rd/IRTo10M5eI+OXI/Ok j5JXi/Tr/wl9MHgf83vHOGbH+cNCkIRl7FEICgSTxHbao8C1kyvZEMTbs9ZO7ahR oQyRW0SelLY3JzkYX7H1XOLMgQ4XY+gVVKGksdugGjgD+yuGbzPKxtHTTP0AAAWD IfAQ/VEO01z+EFGDrPBW =RvtY -----END PGP SIGNATURE----- Merge tag 'meson-clk-for-4.12' of git://github.com/BayLibre/clk-meson into clk-next Pull AmLogic clk driver updates from Jerome Brunet: 2nd Amlogic clock driver update for 4.12: * Protect against holes in onecell_data * Fix divison by zero and overflow in the mpll driver * Add audio clock divider driver for i2s clocks * Add i2s and spdif master clocks
This commit is contained in:
Michael Turquette
commit
a507c57dd1
10
MAINTAINERS
10
MAINTAINERS
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@ -1069,6 +1069,16 @@ F: drivers/pinctrl/meson/
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F: drivers/mmc/host/meson*
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N: meson
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ARM/Amlogic Meson SoC CLOCK FRAMEWORK
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M: Neil Armstrong <narmstrong@baylibre.com>
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M: Jerome Brunet <jbrunet@baylibre.com>
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L: linux-amlogic@lists.infradead.org
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S: Maintained
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F: drivers/clk/meson/
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F: include/dt-bindings/clock/meson*
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F: include/dt-bindings/clock/gxbb*
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F: Documentation/devicetree/bindings/clock/amlogic*
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ARM/Annapurna Labs ALPINE ARCHITECTURE
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M: Tsahee Zidenberg <tsahee@annapurnalabs.com>
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M: Antoine Tenart <antoine.tenart@free-electrons.com>
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@ -2,6 +2,6 @@
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# Makefile for Meson specific clk
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#
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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@ -0,0 +1,144 @@
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/*
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* Copyright (c) 2017 AmLogic, Inc.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* i2s master clock divider: The algorithm of the generic clk-divider used with
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* a very precise clock parent such as the mpll tends to select a low divider
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* factor. This gives poor results with this particular divider, especially with
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* high frequencies (> 100 MHz)
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*
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* This driver try to select the maximum possible divider with the rate the
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* upstream clock can provide.
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*/
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#include <linux/clk-provider.h>
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#include "clkc.h"
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#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
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struct meson_clk_audio_divider, hw)
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static int _div_round(unsigned long parent_rate, unsigned long rate,
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unsigned long flags)
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{
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if (flags & CLK_DIVIDER_ROUND_CLOSEST)
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
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return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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}
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static int _get_val(unsigned long parent_rate, unsigned long rate)
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{
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return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
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}
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static int _valid_divider(struct clk_hw *hw, int divider)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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int max_divider;
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u8 width;
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width = adiv->div.width;
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max_divider = 1 << width;
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return clamp(divider, 1, max_divider);
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}
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static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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struct parm *p;
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unsigned long reg, divider;
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p = &adiv->div;
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reg = readl(adiv->base + p->reg_off);
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divider = PARM_GET(p->width, p->shift, reg) + 1;
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return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
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}
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static long audio_divider_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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unsigned long max_prate;
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int divider;
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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divider = _div_round(*parent_rate, rate, adiv->flags);
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divider = _valid_divider(hw, divider);
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return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
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}
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/* Get the maximum parent rate */
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max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
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/* Get the corresponding rounded down divider */
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divider = max_prate / rate;
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divider = _valid_divider(hw, divider);
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/* Get actual rate of the parent */
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*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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divider * rate);
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return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
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}
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static int audio_divider_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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struct parm *p;
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unsigned long reg, flags = 0;
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int val;
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val = _get_val(parent_rate, rate);
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if (adiv->lock)
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spin_lock_irqsave(adiv->lock, flags);
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else
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__acquire(adiv->lock);
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p = &adiv->div;
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reg = readl(adiv->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, val);
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writel(reg, adiv->base + p->reg_off);
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if (adiv->lock)
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spin_unlock_irqrestore(adiv->lock, flags);
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else
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__release(adiv->lock);
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return 0;
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}
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const struct clk_ops meson_clk_audio_divider_ro_ops = {
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.recalc_rate = audio_divider_recalc_rate,
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.round_rate = audio_divider_round_rate,
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};
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const struct clk_ops meson_clk_audio_divider_ops = {
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.recalc_rate = audio_divider_recalc_rate,
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.round_rate = audio_divider_round_rate,
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.set_rate = audio_divider_set_rate,
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};
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@ -65,18 +65,21 @@
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#include "clkc.h"
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#define SDM_DEN 16384
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#define SDM_MIN 1
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#define SDM_MAX 16383
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#define N2_MIN 4
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#define N2_MAX 511
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#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
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static unsigned long rate_from_params(unsigned long parent_rate,
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static long rate_from_params(unsigned long parent_rate,
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unsigned long sdm,
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unsigned long n2)
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{
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return (parent_rate * SDM_DEN) / ((SDM_DEN * n2) + sdm);
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unsigned long divisor = (SDM_DEN * n2) + sdm;
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if (n2 < N2_MIN)
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return -EINVAL;
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return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
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}
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static void params_from_rate(unsigned long requested_rate,
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@ -89,17 +92,13 @@ static void params_from_rate(unsigned long requested_rate,
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if (div < N2_MIN) {
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*n2 = N2_MIN;
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*sdm = SDM_MIN;
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*sdm = 0;
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} else if (div > N2_MAX) {
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*n2 = N2_MAX;
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*sdm = SDM_MAX;
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*sdm = SDM_DEN - 1;
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} else {
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*n2 = div;
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*sdm = DIV_ROUND_UP(rem * SDM_DEN, requested_rate);
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if (*sdm < SDM_MIN)
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*sdm = SDM_MIN;
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else if (*sdm > SDM_MAX)
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*sdm = SDM_MAX;
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}
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}
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@ -109,6 +108,7 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
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struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
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struct parm *p;
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unsigned long reg, sdm, n2;
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long rate;
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p = &mpll->sdm;
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reg = readl(mpll->base + p->reg_off);
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@ -118,7 +118,11 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
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reg = readl(mpll->base + p->reg_off);
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n2 = PARM_GET(p->width, p->shift, reg);
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return rate_from_params(parent_rate, sdm, n2);
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rate = rate_from_params(parent_rate, sdm, n2);
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if (rate < 0)
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return 0;
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return rate;
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}
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static long mpll_round_rate(struct clk_hw *hw,
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@ -121,6 +121,14 @@ struct meson_clk_mpll {
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spinlock_t *lock;
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};
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struct meson_clk_audio_divider {
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struct clk_hw hw;
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void __iomem *base;
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struct parm div;
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u8 flags;
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spinlock_t *lock;
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};
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#define MESON_GATE(_name, _reg, _bit) \
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struct clk_gate _name = { \
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.reg = (void __iomem *) _reg, \
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@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
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extern const struct clk_ops meson_clk_cpu_ops;
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extern const struct clk_ops meson_clk_mpll_ro_ops;
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extern const struct clk_ops meson_clk_mpll_ops;
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extern const struct clk_ops meson_clk_audio_divider_ro_ops;
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extern const struct clk_ops meson_clk_audio_divider_ops;
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#endif /* __CLKC_H */
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@ -845,6 +845,112 @@ static struct clk_mux gxbb_mali = {
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},
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};
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static struct clk_mux gxbb_cts_amclk_sel = {
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.reg = (void *) HHI_AUD_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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/* Default parent unknown (register reset value: 0) */
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.table = (u32[]){ 1, 2, 3 },
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk_sel",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
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.num_parents = 3,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
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.div = {
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.reg_off = HHI_AUD_CLK_CNTL,
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.shift = 0,
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.width = 8,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk_div",
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.ops = &meson_clk_audio_divider_ops,
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.parent_names = (const char *[]){ "cts_amclk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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},
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};
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static struct clk_gate gxbb_cts_amclk = {
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.reg = (void *) HHI_AUD_CLK_CNTL,
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.bit_idx = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "cts_amclk_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_mux gxbb_cts_mclk_i958_sel = {
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.reg = (void *)HHI_AUD_CLK_CNTL2,
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.mask = 0x3,
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.shift = 25,
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/* Default parent unknown (register reset value: 0) */
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.table = (u32[]){ 1, 2, 3 },
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.lock = &clk_lock,
|
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.hw.init = &(struct clk_init_data){
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.name = "cts_mclk_i958_sel",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
|
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.num_parents = 3,
|
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.flags = CLK_SET_RATE_PARENT,
|
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},
|
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};
|
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|
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static struct clk_divider gxbb_cts_mclk_i958_div = {
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.reg = (void *)HHI_AUD_CLK_CNTL2,
|
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.shift = 16,
|
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.width = 8,
|
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.lock = &clk_lock,
|
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.hw.init = &(struct clk_init_data){
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.name = "cts_mclk_i958_div",
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.ops = &clk_divider_ops,
|
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.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
|
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.num_parents = 1,
|
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
|
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},
|
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};
|
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|
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static struct clk_gate gxbb_cts_mclk_i958 = {
|
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.reg = (void *)HHI_AUD_CLK_CNTL2,
|
||||
.bit_idx = 24,
|
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.lock = &clk_lock,
|
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.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_mclk_i958",
|
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.ops = &clk_gate_ops,
|
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.parent_names = (const char *[]){ "cts_mclk_i958_div" },
|
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.num_parents = 1,
|
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.flags = CLK_SET_RATE_PARENT,
|
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},
|
||||
};
|
||||
|
||||
static struct clk_mux gxbb_cts_i958 = {
|
||||
.reg = (void *)HHI_AUD_CLK_CNTL2,
|
||||
.mask = 0x1,
|
||||
.shift = 27,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_i958",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
|
||||
.num_parents = 2,
|
||||
/*
|
||||
*The parent is specific to origin of the audio data. Let the
|
||||
* consumer choose the appropriate parent
|
||||
*/
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
|
||||
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
|
||||
|
|
@ -1045,6 +1151,13 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
|||
[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &gxbb_mali_1.hw,
|
||||
[CLKID_MALI] = &gxbb_mali.hw,
|
||||
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
|
@ -1158,6 +1271,13 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
|
|||
[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &gxbb_mali_1.hw,
|
||||
[CLKID_MALI] = &gxbb_mali.hw,
|
||||
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
|
@ -1270,6 +1390,8 @@ static struct clk_gate *const gxbb_clk_gates[] = {
|
|||
&gxbb_sar_adc_clk,
|
||||
&gxbb_mali_0,
|
||||
&gxbb_mali_1,
|
||||
&gxbb_cts_amclk,
|
||||
&gxbb_cts_mclk_i958,
|
||||
};
|
||||
|
||||
static struct clk_mux *const gxbb_clk_muxes[] = {
|
||||
|
|
@ -1278,6 +1400,9 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
|
|||
&gxbb_mali_0_sel,
|
||||
&gxbb_mali_1_sel,
|
||||
&gxbb_mali,
|
||||
&gxbb_cts_amclk_sel,
|
||||
&gxbb_cts_mclk_i958_sel,
|
||||
&gxbb_cts_i958,
|
||||
};
|
||||
|
||||
static struct clk_divider *const gxbb_clk_dividers[] = {
|
||||
|
|
@ -1285,6 +1410,11 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
|
|||
&gxbb_sar_adc_clk_div,
|
||||
&gxbb_mali_0_div,
|
||||
&gxbb_mali_1_div,
|
||||
&gxbb_cts_mclk_i958_div,
|
||||
};
|
||||
|
||||
static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
|
||||
&gxbb_cts_amclk_div,
|
||||
};
|
||||
|
||||
struct clkc_data {
|
||||
|
|
@ -1298,6 +1428,8 @@ struct clkc_data {
|
|||
unsigned int clk_muxes_count;
|
||||
struct clk_divider *const *clk_dividers;
|
||||
unsigned int clk_dividers_count;
|
||||
struct meson_clk_audio_divider *const *clk_audio_dividers;
|
||||
unsigned int clk_audio_dividers_count;
|
||||
struct meson_clk_cpu *cpu_clk;
|
||||
struct clk_hw_onecell_data *hw_onecell_data;
|
||||
};
|
||||
|
|
@ -1313,6 +1445,8 @@ static const struct clkc_data gxbb_clkc_data = {
|
|||
.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
|
||||
.clk_dividers = gxbb_clk_dividers,
|
||||
.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
|
||||
.clk_audio_dividers = gxbb_audio_dividers,
|
||||
.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
|
||||
.cpu_clk = &gxbb_cpu_clk,
|
||||
.hw_onecell_data = &gxbb_hw_onecell_data,
|
||||
};
|
||||
|
|
@ -1328,6 +1462,8 @@ static const struct clkc_data gxl_clkc_data = {
|
|||
.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
|
||||
.clk_dividers = gxbb_clk_dividers,
|
||||
.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
|
||||
.clk_audio_dividers = gxbb_audio_dividers,
|
||||
.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
|
||||
.cpu_clk = &gxbb_cpu_clk,
|
||||
.hw_onecell_data = &gxl_hw_onecell_data,
|
||||
};
|
||||
|
|
@ -1384,10 +1520,18 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
|
|||
clkc_data->clk_dividers[i]->reg = clk_base +
|
||||
(u64)clkc_data->clk_dividers[i]->reg;
|
||||
|
||||
/* Populate base address for the audio dividers */
|
||||
for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
|
||||
clkc_data->clk_audio_dividers[i]->base = clk_base;
|
||||
|
||||
/*
|
||||
* register all clks
|
||||
*/
|
||||
for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
|
||||
/* array might be sparse */
|
||||
if (!clkc_data->hw_onecell_data->hws[clkid])
|
||||
continue;
|
||||
|
||||
ret = devm_clk_hw_register(dev,
|
||||
clkc_data->hw_onecell_data->hws[clkid]);
|
||||
if (ret)
|
||||
|
|
|
|||
|
|
@ -277,8 +277,15 @@
|
|||
#define CLKID_MALI_1_DIV 104
|
||||
/* CLKID_MALI_1 */
|
||||
/* CLKID_MALI */
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_AMCLK_SEL 108
|
||||
#define CLKID_CTS_AMCLK_DIV 109
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_MCLK_I958_SEL 111
|
||||
#define CLKID_CTS_MCLK_I958_DIV 112
|
||||
#define CLKID_CTS_I958 113
|
||||
|
||||
#define NR_CLKS 107
|
||||
#define NR_CLKS 114
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue