x86/gpu: Add Intel graphics stolen memory quirk for gen2 platforms
There isn't an explicit stolen memory base register on gen2. Some old comment in the i915 code suggests we should get it via max_low_pfn_mapped, but that's clearly a bad idea on my MGM. The e820 map in said machine looks like this: BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory would start there would place it on top of some ACPI memory regions. So not a good idea as already stated. The 9MB region after the ACPI regions at 0x1f700000 however looks promising given that the macine reports the stolen memory size to be 8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset 0x1fee00000, and given that the GTT entries occupy 128KB, it looks like the stolen memory could start at 0x1f700000 and the GTT entries would occupy the last 128KB of the stolen memory. After some more digging through chipset documentation, I've determined the BIOS first allocates space for something called TSEG (something to do with SMM) from the top of memory, and then it allocates the graphics stolen memory below that. Accordind to the chipset documentation TSEG has a fixed size of 1MB on 855. So that explains the top 1MB in the e820 region. And it also confirms that the GTT entries are in fact at the end of the the stolen memory region. Derive the stolen memory base address on gen2 the same as the BIOS does (TOM-TSEG_SIZE-stolen_size). There are a few differences between the registers on various gen2 chipsets, so a few different codepaths are required. 865G is again bit more special since it seems to support enough memory to hit 4GB address space issues. This means the PCI allocations will also affect the location of the stolen memory. Fortunately there appears to be the TOUD register which may give us the correct answer directly. But the chipset docs are a bit unclear, so I'm not 100% sure that the graphics stolen memory is always the last thing the BIOS steals. Someone would need to verify it on a real system. I tested this on the my 830 and 855 machines, and so far everything looks peachy. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Link: http://lkml.kernel.org/r/1391628540-23072-3-git-send-email-ville.syrjala@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ville Syrjälä
Ingo Molnar
parent
52ca70454e
commit
a4dff76924
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@ -247,6 +247,114 @@ static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_s
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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static size_t __init i830_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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if (tmp & I830_TSEG_SIZE_1M)
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return MB(1);
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else
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return KB(512);
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}
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static size_t __init i845_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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switch (tmp & I845_TSEG_SIZE_MASK) {
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case I845_TSEG_SIZE_512K:
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return KB(512);
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case I845_TSEG_SIZE_1M:
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return MB(1);
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default:
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WARN_ON(1);
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return 0;
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}
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}
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static size_t __init i85x_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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return MB(1);
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}
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static size_t __init i830_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
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}
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static size_t __init i85x_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
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}
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/*
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* On 830/845/85x the stolen memory base isn't available in any
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* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
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*/
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static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i830_mem_size() - i830_tseg_size() - stolen_size;
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}
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static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i830_mem_size() - i845_tseg_size() - stolen_size;
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}
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static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i85x_mem_size() - i85x_tseg_size() - stolen_size;
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}
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static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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/*
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* FIXME is the graphics stolen memory region
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* always at TOUD? Ie. is it always the last
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* one to be allocated by the BIOS?
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*/
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return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
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}
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static size_t __init i830_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
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case I830_GMCH_GMS_STOLEN_512:
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stolen_size = KB(512);
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break;
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case I830_GMCH_GMS_STOLEN_1024:
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stolen_size = MB(1);
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break;
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case I830_GMCH_GMS_STOLEN_8192:
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stolen_size = MB(8);
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break;
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case I830_GMCH_GMS_LOCAL:
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/* local memory isn't part of the normal address space */
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stolen_size = 0;
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break;
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default:
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return 0;
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}
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return stolen_size;
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}
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static size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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@ -329,6 +437,26 @@ struct intel_stolen_funcs {
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u32 (*base)(int num, int slot, int func, size_t size);
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};
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static const struct intel_stolen_funcs i830_stolen_funcs = {
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.base = i830_stolen_base,
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.size = i830_stolen_size,
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};
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static const struct intel_stolen_funcs i845_stolen_funcs = {
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.base = i845_stolen_base,
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.size = i830_stolen_size,
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};
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static const struct intel_stolen_funcs i85x_stolen_funcs = {
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.base = i85x_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs i865_stolen_funcs = {
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.base = i865_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs gen3_stolen_funcs = {
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.base = intel_stolen_base,
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.size = gen3_stolen_size,
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@ -345,6 +473,10 @@ static const struct intel_stolen_funcs gen8_stolen_funcs = {
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};
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static struct pci_device_id intel_stolen_ids[] __initdata = {
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INTEL_I830_IDS(&i830_stolen_funcs),
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INTEL_I845G_IDS(&i845_stolen_funcs),
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INTEL_I85X_IDS(&i85x_stolen_funcs),
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INTEL_I865G_IDS(&i865_stolen_funcs),
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INTEL_I915G_IDS(&gen3_stolen_funcs),
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INTEL_I915GM_IDS(&gen3_stolen_funcs),
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INTEL_I945G_IDS(&gen3_stolen_funcs),
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@ -56,6 +56,12 @@ extern bool i915_gpu_turbo_disable(void);
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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@ -72,4 +78,18 @@ extern bool i915_gpu_turbo_disable(void);
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I830_DRB3 0x63
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#define I85X_DRB3 0x43
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#define I865_TOUD 0xc4
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#define I830_ESMRAMC 0x91
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#define I845_ESMRAMC 0x9e
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#define I85X_ESMRAMC 0x61
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#define TSEG_ENABLE (1 << 0)
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#define I830_TSEG_SIZE_512K (0 << 1)
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#define I830_TSEG_SIZE_1M (1 << 1)
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#define I845_TSEG_SIZE_MASK (3 << 1)
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#define I845_TSEG_SIZE_512K (2 << 1)
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#define I845_TSEG_SIZE_1M (3 << 1)
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#endif /* _I915_DRM_H_ */
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