mmc: sdhci-of-esdhc: add erratum eSDHC5 support
Software writing to the Transfer Type configuration register (system clock domain) can cause a setup/hold violation in the CRC flops (card clock domain), which can cause write accesses to be sent with corrupt CRC values. This issue occurs only for write preceded by read. this erratum is to fix this issue. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -1075,6 +1075,9 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
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if (esdhc->vendor_ver > VENDOR_V_22)
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if (esdhc->vendor_ver > VENDOR_V_22)
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host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
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host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
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if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc"))
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host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
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if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
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if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
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of_device_is_compatible(np, "fsl,p5020-esdhc") ||
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of_device_is_compatible(np, "fsl,p5020-esdhc") ||
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of_device_is_compatible(np, "fsl,p4080-esdhc") ||
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of_device_is_compatible(np, "fsl,p4080-esdhc") ||
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