Create msi-x whitelist,turn on msi-x for top intr

Turn on msi-x for top intr. Create msi-x whitelist,
Limited the number of msi-x interrupts for inter x520 and wangxun NIC.

Signed-off-by: chengjun.li <chengjun.li@sophgo.com>

arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi

@@ -19,7 +19,7 @@
 		link-id = /bits/ 16 <0x0>;
 		top-intc-used = <1>;
 		top-intc-id = <0>;
-		msix-supported = <0>;
+		msix-supported = <1>;
 		interrupt-parent = <&intc1>;
 		//interrupts = <SOC_PERIPHERAL_IRQ(123) IRQ_TYPE_LEVEL_HIGH>;
 		//interrupt-names = "msi";

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

@@ -2069,7 +2069,7 @@ enum {
 #define IXGBE_DEVICE_CAPS       0x2C
 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
 #define IXGBE_PCIE_MSIX_82599_CAPS  0x72
-#define IXGBE_MAX_MSIX_VECTORS_82599	0x40
+#define IXGBE_MAX_MSIX_VECTORS_82599	0x09
 #define IXGBE_PCIE_MSIX_82598_CAPS  0x62
 #define IXGBE_MAX_MSIX_VECTORS_82598	0x13
 

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

@@ -1728,7 +1728,7 @@ enum TXGBE_MSCA_CMD_value {
 #define TXGBE_ISCSI_BOOT_CONFIG         0x07
 
 #define TXGBE_SERIAL_NUMBER_MAC_ADDR    0x11
-#define TXGBE_MAX_MSIX_VECTORS_SAPPHIRE 0x40
+#define TXGBE_MAX_MSIX_VECTORS_SAPPHIRE 0x09
 
 /* MSI-X capability fields masks */
 #define TXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF

drivers/pci/controller/cadence/pcie-cadence-sophgo.c

@@ -456,10 +456,37 @@ static struct msi_domain_info cdns_pcie_msi_domain_info = {
 
 static struct msi_domain_info cdns_pcie_top_intr_msi_domain_info = {
 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS
-		   | MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
+		   | MSI_FLAG_PCI_MSIX),
 	.chip	= &cdns_pcie_msi_irq_chip,
 };
 
+struct vendor_id_list vendor_id_list[] = {
+	{"Inter X520", 0x8086},
+	{"WangXun RP1000", 0x8088},
+};
+
+size_t vendor_id_list_num = ARRAY_SIZE(vendor_id_list);
+
+int check_vendor_id(struct pci_dev *dev, struct vendor_id_list vendor_id_list[],
+			size_t vendor_id_list_num)
+{
+	uint16_t device_vendor_id;
+
+	if (pci_read_config_word(dev, PCI_VENDOR_ID, &device_vendor_id) != 0) {
+		pr_err("Failed to read device vendor ID\n");
+		return 0;
+	}
+
+	for (int i = 0; i < vendor_id_list_num; ++i) {
+		if (device_vendor_id == vendor_id_list[i].vendor_id) {
+			pr_info("dev: %s vendor ID: 0x%04x Enable MSI-X IRQ\n",
+				vendor_id_list[i].name, device_vendor_id);
+			return 1;
+		}
+	}
+	return 0;
+}
+
 static int cdns_pcie_msi_setup_for_top_intc(struct cdns_mango_pcie_rc *rc, int intc_id)
 {
 	struct irq_domain *irq_parent = cdns_pcie_get_parent_irq_domain(intc_id);
@@ -469,12 +496,10 @@ static int cdns_pcie_msi_setup_for_top_intc(struct cdns_mango_pcie_rc *rc, int i
 		rc->msi_domain = pci_msi_create_irq_domain(fwnode,
 							   &cdns_pcie_top_intr_msi_domain_info,
 							   irq_parent);
-
 	} else {
 		rc->msi_domain = pci_msi_create_irq_domain(fwnode,
 							   &cdns_pcie_msi_domain_info,
 							   irq_parent);
-
 	}
 
 	if (!rc->msi_domain) {

drivers/pci/controller/cadence/pcie-cadence-sophgo.h

@@ -1,6 +1,16 @@
 #ifndef PCIE_CADENCE_SOPHGO
 #define PCIE_CADENCE_SOPHGO
 
-extern struct irq_domain *cdns_pcie_get_parent_irq_domain(int intc_id);
 
+struct vendor_id_list {
+	const char  *name;
+	uint16_t    vendor_id;
+};
+
+extern struct vendor_id_list vendor_id_list[];
+extern size_t vendor_id_list_num;
+
+extern struct irq_domain *cdns_pcie_get_parent_irq_domain(int intc_id);
+int check_vendor_id(struct pci_dev *dev, struct vendor_id_list vendor_id_list[],
+			size_t vendor_id_list_num);
 #endif

drivers/pci/msi/msi.c

@@ -12,6 +12,7 @@
 
 #include "../pci.h"
 #include "msi.h"
+#include "../controller/cadence/pcie-cadence-sophgo.h"
 
 static int pci_msi_enable = 1;
 int pci_msi_ignore_mask;
@@ -932,33 +933,37 @@ static int __pci_enable_msix_range(struct pci_dev *dev,
 {
 	int rc, nvec = maxvec;
 
-	if (maxvec < minvec)
-		return -ERANGE;
+	if (check_vendor_id(dev, vendor_id_list, vendor_id_list_num)) {
+		if (maxvec < minvec)
+			return -ERANGE;
 
-	if (WARN_ON_ONCE(dev->msix_enabled))
-		return -EINVAL;
+		if (WARN_ON_ONCE(dev->msix_enabled))
+			return -EINVAL;
 
-	rc = pci_setup_msi_context(dev);
-	if (rc)
-		return rc;
-
-	for (;;) {
-		if (affd) {
-			nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
-			if (nvec < minvec)
-				return -ENOSPC;
-		}
-
-		rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
-		if (rc == 0)
-			return nvec;
-
-		if (rc < 0)
+		rc = pci_setup_msi_context(dev);
+		if (rc)
 			return rc;
-		if (rc < minvec)
-			return -ENOSPC;
 
-		nvec = rc;
+		for (;;) {
+			if (affd) {
+				nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
+				if (nvec < minvec)
+					return -ENOSPC;
+			}
+
+			rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
+			if (rc == 0)
+				return nvec;
+
+			if (rc < 0)
+				return rc;
+			if (rc < minvec)
+				return -ENOSPC;
+
+			nvec = rc;
+		}
+	} else {
+		return -1;
 	}
 }