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Renesas driver updates for v5.9 

- Add core support for the new RZ/G2H (R8A774E1) SoC, including System
     Controller (SYSC) and Reset (RST) support.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXxFlJQAKCRCKwlD9ZEnx
 cBc5AQDuPW0JS4eKE+oARQ3EMxw3ZrEA1zzleiML19YnvEy5YgEA0UsdDlPGnRs1
 dZruiWUH9xu4n7zWVZshKf2BBSSTWw0=
 =+Zex
 -----END PGP SIGNATURE-----

Merge tag 'renesas-drivers-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.9

  - Add core support for the new RZ/G2H (R8A774E1) SoC, including System
    Controller (SYSC) and Reset (RST) support.

* tag 'renesas-drivers-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-rst: Add support for RZ/G2H
  soc: renesas: Identify RZ/G2H
  soc: renesas: Add Renesas R8A774E1 config option
  soc: renesas: rcar-sysc: Add r8a774e1 support
  clk: renesas: Add r8a774e1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774e1 SYSC power domain definitions

Link: https://lore.kernel.org/r/20200717112427.26032-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-07-17 16:06:25 +02:00
parent 7247e1f1b0 7f8fa833dc
commit a3cff3e6ed
9 changed files with 163 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/soc/renesas/Kconfig
View File

@ -201,6 +201,13 @@ config ARCH_R8A774C0
help
This enables support for the Renesas RZ/G2E SoC.
config ARCH_R8A774E1
bool "Renesas RZ/G2H SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A774E1
help
This enables support for the Renesas RZ/G2H SoC.
config ARCH_R8A77950
bool "Renesas R-Car H3 ES1.x SoC Platform"
select ARCH_RCAR_GEN3
@ -296,6 +303,10 @@ config SYSC_R8A774C0
bool "RZ/G2E System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A774E1
bool "RZ/G2H System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A7779
bool "R-Car H1 System Controller support" if COMPILE_TEST
select SYSC_RCAR

1
drivers/soc/renesas/Makefile
View File

@ -10,6 +10,7 @@ obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o
obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o
obj-$(CONFIG_SYSC_R8A774E1) += r8a774e1-sysc.o
obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o
obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o

43
drivers/soc/renesas/r8a774e1-sysc.c Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/G2H System Controller
* Copyright (C) 2020 Renesas Electronics Corp.
*
* Based on Renesas R-Car H3 System Controller
* Copyright (C) 2016-2017 Glider bvba
*/
#include <linux/kernel.h>
#include <dt-bindings/power/r8a774e1-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a774e1_areas[] __initconst = {
{ "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
{ "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
{ "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
{ "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
{ "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
{ "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
{ "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
{ "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
{ "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
{ "ca53-cpu3", 0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
{ "a3vp", 0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON },
{ "a3vc", 0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON },
{ "a2vc1", 0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC },
{ "3dg-a", 0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON },
{ "3dg-b", 0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A },
{ "3dg-c", 0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B },
{ "3dg-d", 0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C },
{ "3dg-e", 0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D },
};
const struct rcar_sysc_info r8a774e1_sysc_info __initconst = {
.areas = r8a774e1_areas,
.num_areas = ARRAY_SIZE(r8a774e1_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

1
drivers/soc/renesas/rcar-rst.c
View File

@ -48,6 +48,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen1 */
{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },

3
drivers/soc/renesas/rcar-sysc.c
View File

@ -296,6 +296,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A774C0
{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A774E1
{ .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A7779
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
#endif

1
drivers/soc/renesas/rcar-sysc.h
View File

@ -56,6 +56,7 @@ extern const struct rcar_sysc_info r8a77470_sysc_info;
extern const struct rcar_sysc_info r8a774a1_sysc_info;
extern const struct rcar_sysc_info r8a774b1_sysc_info;
extern const struct rcar_sysc_info r8a774c0_sysc_info;
extern const struct rcar_sysc_info r8a774e1_sysc_info;
extern const struct rcar_sysc_info r8a7779_sysc_info;
extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info;

8
drivers/soc/renesas/renesas-soc.c
View File

@ -126,6 +126,11 @@ static const struct renesas_soc soc_rz_g2e __initconst __maybe_unused = {
.id = 0x57,
};
static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x4f,
};
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
@ -238,6 +243,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A774C0
{ .compatible = "renesas,r8a774c0", .data = &soc_rz_g2e },
#endif
#ifdef CONFIG_ARCH_R8A774E1
{ .compatible = "renesas,r8a774e1", .data = &soc_rz_g2h },
#endif
#ifdef CONFIG_ARCH_R8A7778
{ .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a },
#endif

59
include/dt-bindings/clock/r8a774e1-cpg-mssr.h Normal file
View File

@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R8A774E1 CPG Core Clocks */
#define R8A774E1_CLK_Z 0
#define R8A774E1_CLK_Z2 1
#define R8A774E1_CLK_ZG 2
#define R8A774E1_CLK_ZTR 3
#define R8A774E1_CLK_ZTRD2 4
#define R8A774E1_CLK_ZT 5
#define R8A774E1_CLK_ZX 6
#define R8A774E1_CLK_S0D1 7
#define R8A774E1_CLK_S0D2 8
#define R8A774E1_CLK_S0D3 9
#define R8A774E1_CLK_S0D4 10
#define R8A774E1_CLK_S0D6 11
#define R8A774E1_CLK_S0D8 12
#define R8A774E1_CLK_S0D12 13
#define R8A774E1_CLK_S1D2 14
#define R8A774E1_CLK_S1D4 15
#define R8A774E1_CLK_S2D1 16
#define R8A774E1_CLK_S2D2 17
#define R8A774E1_CLK_S2D4 18
#define R8A774E1_CLK_S3D1 19
#define R8A774E1_CLK_S3D2 20
#define R8A774E1_CLK_S3D4 21
#define R8A774E1_CLK_LB 22
#define R8A774E1_CLK_CL 23
#define R8A774E1_CLK_ZB3 24
#define R8A774E1_CLK_ZB3D2 25
#define R8A774E1_CLK_ZB3D4 26
#define R8A774E1_CLK_CR 27
#define R8A774E1_CLK_CRD2 28
#define R8A774E1_CLK_SD0H 29
#define R8A774E1_CLK_SD0 30
#define R8A774E1_CLK_SD1H 31
#define R8A774E1_CLK_SD1 32
#define R8A774E1_CLK_SD2H 33
#define R8A774E1_CLK_SD2 34
#define R8A774E1_CLK_SD3H 35
#define R8A774E1_CLK_SD3 36
#define R8A774E1_CLK_RPC 37
#define R8A774E1_CLK_RPCD2 38
#define R8A774E1_CLK_MSO 39
#define R8A774E1_CLK_HDMI 40
#define R8A774E1_CLK_CSI0 41
#define R8A774E1_CLK_CP 42
#define R8A774E1_CLK_CPEX 43
#define R8A774E1_CLK_R 44
#define R8A774E1_CLK_OSC 45
#define R8A774E1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */

36
include/dt-bindings/power/r8a774e1-sysc.h Normal file
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@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774E1_PD_CA57_CPU0 0
#define R8A774E1_PD_CA57_CPU1 1
#define R8A774E1_PD_CA57_CPU2 2
#define R8A774E1_PD_CA57_CPU3 3
#define R8A774E1_PD_CA53_CPU0 5
#define R8A774E1_PD_CA53_CPU1 6
#define R8A774E1_PD_CA53_CPU2 7
#define R8A774E1_PD_CA53_CPU3 8
#define R8A774E1_PD_A3VP 9
#define R8A774E1_PD_CA57_SCU 12
#define R8A774E1_PD_A3VC 14
#define R8A774E1_PD_3DG_A 17
#define R8A774E1_PD_3DG_B 18
#define R8A774E1_PD_3DG_C 19
#define R8A774E1_PD_3DG_D 20
#define R8A774E1_PD_CA53_SCU 21
#define R8A774E1_PD_3DG_E 22
#define R8A774E1_PD_A2VC1 26
/* Always-on power area */
#define R8A774E1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */