[MIPS] SB1: Fix interrupt disable hazard.
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
3a2f735700
commit
a3c4946db4
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@ -3,7 +3,9 @@
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* License. See the file "COPYING" in the main directory of this archive
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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* for more details.
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*
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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*/
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#ifndef _ASM_HAZARDS_H
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#ifndef _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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@ -74,8 +76,7 @@
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#define irq_disable_hazard
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#define irq_disable_hazard
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_ehb
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_ehb
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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defined(CONFIG_CPU_SB1)
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/*
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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@ -99,13 +100,13 @@
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#else /* __ASSEMBLY__ */
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#else /* __ASSEMBLY__ */
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__asm__(
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__asm__(
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" .macro _ssnop \n\t"
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" .macro _ssnop \n"
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" sll $0, $0, 1 \n\t"
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" sll $0, $0, 1 \n"
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" .endm \n\t"
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" .endm \n"
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" \n\t"
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" \n"
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" .macro _ehb \n\t"
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" .macro _ehb \n"
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" sll $0, $0, 3 \n\t"
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" sll $0, $0, 3 \n"
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" .endm \n\t");
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" .endm \n");
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#ifdef CONFIG_CPU_RM9000
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#ifdef CONFIG_CPU_RM9000
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@ -117,17 +118,21 @@ __asm__(
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#define mtc0_tlbw_hazard() \
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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" .set mips32 \n" \
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"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
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" _ssnop \n" \
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".set\tmips0")
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" _ssnop \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" .set mips0 \n")
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#define tlbw_use_hazard() \
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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" .set mips32 \n" \
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"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
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" _ssnop \n" \
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".set\tmips0")
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" _ssnop \n" \
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" _ssnop \n" \
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#define back_to_back_c0_hazard() do { } while (0)
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" _ssnop \n" \
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" .set mips0 \n")
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#else
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#else
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@ -136,15 +141,25 @@ __asm__(
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*/
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*/
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#define mtc0_tlbw_hazard() \
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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" .set noreorder \n" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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" nop \n" \
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".set reorder\n\t")
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" .set reorder \n")
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#define tlbw_use_hazard() \
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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" .set noreorder \n" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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" nop \n" \
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".set reorder\n\t")
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" .set reorder \n")
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#endif
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#endif
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@ -156,49 +171,26 @@ __asm__(
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#ifdef CONFIG_CPU_MIPSR2
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#ifdef CONFIG_CPU_MIPSR2
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__asm__(
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__asm__(" .macro irq_enable_hazard \n"
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" .macro\tirq_enable_hazard \n\t"
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" _ehb \n"
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" _ehb \n\t"
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" .endm \n"
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" .endm \n\t"
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" \n"
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" \n\t"
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" .macro irq_disable_hazard \n"
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" .macro\tirq_disable_hazard \n\t"
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" _ehb \n"
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" _ehb \n\t"
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" .endm \n");
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" .endm \n\t"
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" \n\t"
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" .macro\tback_to_back_c0_hazard \n\t"
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" _ehb \n\t"
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" .endm");
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#define irq_enable_hazard() \
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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__asm__ __volatile__( \
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"irq_enable_hazard")
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#define irq_disable_hazard() \
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__asm__ __volatile__( \
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"irq_disable_hazard")
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#define back_to_back_c0_hazard() \
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__asm__ __volatile__( \
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"back_to_back_c0_hazard")
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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defined(CONFIG_CPU_SB1)
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/*
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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*/
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__asm__(
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__asm__(
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" .macro\tirq_enable_hazard \n\t"
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" .macro irq_enable_hazard \n"
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" .endm \n\t"
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" .endm \n"
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" \n\t"
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" \n"
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" .macro\tirq_disable_hazard \n\t"
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" .macro irq_disable_hazard \n"
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" .endm");
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" .endm \n");
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#define irq_enable_hazard() do { } while (0)
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#define irq_disable_hazard() do { } while (0)
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#define back_to_back_c0_hazard() do { } while (0)
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#else
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#else
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@ -209,29 +201,63 @@ __asm__(
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*/
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*/
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__asm__(
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__asm__(
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" # \n\t"
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" # \n"
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" # There is a hazard but we do not care \n\t"
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" # There is a hazard but we do not care \n"
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" # \n\t"
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" # \n"
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" .macro\tirq_enable_hazard \n\t"
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" .macro\tirq_enable_hazard \n"
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" .endm \n\t"
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" .endm \n"
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" \n\t"
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" \n"
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" .macro\tirq_disable_hazard \n\t"
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" .macro\tirq_disable_hazard \n"
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" _ssnop; _ssnop; _ssnop \n\t"
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" _ssnop \n"
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" .endm");
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" _ssnop \n"
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" _ssnop \n"
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#define irq_enable_hazard() do { } while (0)
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" .endm \n");
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#define irq_disable_hazard() \
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__asm__ __volatile__( \
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"irq_disable_hazard")
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#define back_to_back_c0_hazard() \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" nop; nop; nop \n" \
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" .set reorder \n")
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#endif
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#endif
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#define irq_enable_hazard() \
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__asm__ __volatile__("irq_enable_hazard")
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#define irq_disable_hazard() \
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__asm__ __volatile__("irq_disable_hazard")
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/*
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* Back-to-back hazards -
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*
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* What is needed to separate a move to cp0 from a subsequent read from the
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* same cp0 register?
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*/
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#ifdef CONFIG_CPU_MIPSR2
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__asm__(" .macro back_to_back_c0_hazard \n"
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" _ehb \n"
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" .endm \n");
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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defined(CONFIG_CPU_SB1)
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__asm__(" .macro back_to_back_c0_hazard \n"
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" .endm \n");
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#else
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__asm__(" .macro back_to_back_c0_hazard \n"
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" .set noreorder \n"
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" _ssnop \n"
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" _ssnop \n"
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" _ssnop \n"
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" .set reorder \n"
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" .endm");
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#endif
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#define back_to_back_c0_hazard() \
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__asm__ __volatile__("back_to_back_c0_hazard")
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/*
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* Instruction execution hazard
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*/
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#ifdef CONFIG_CPU_MIPSR2
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#ifdef CONFIG_CPU_MIPSR2
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/*
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/*
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* gcc has a tradition of misscompiling the previous construct using the
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* gcc has a tradition of misscompiling the previous construct using the
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