MIPS: atomic: Use one macro to generate 32b & 64b functions
Cut down on duplication by generalizing the ATOMIC_OP(), ATOMIC_OP_RETURN() & ATOMIC_FETCH_OP() macros to work for both 32b & 64b atomics, and removing the ATOMIC64_ variants. This ensures consistency between our atomic_* & atomic64_* functions. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Paul Burton
parent
9537db24c6
commit
a38ee6bb14
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@ -42,10 +42,10 @@
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*/
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#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC_OP(op, c_op, asm_op) \
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static __inline__ void atomic_##op(int i, atomic_t * v) \
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#define ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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static __inline__ void pfx##_##op(type i, pfx##_t * v) \
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{ \
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int temp; \
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type temp; \
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\
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if (!kernel_uses_llsc) { \
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unsigned long flags; \
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@ -60,19 +60,19 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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"1: ll %0, %1 # atomic_" #op " \n" \
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"1: " #ll " %0, %1 # " #pfx "_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" sc %0, %1 \n" \
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" " #sc " %0, %1 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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" .set pop \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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}
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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#define ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
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static __inline__ type pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
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{ \
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int temp, result; \
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type temp, result; \
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\
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if (!kernel_uses_llsc) { \
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unsigned long flags; \
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@ -89,9 +89,9 @@ static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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"1: ll %1, %2 # atomic_" #op "_return \n" \
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"1: " #ll " %1, %2 # " #pfx "_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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" " #sc " %0, %2 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set pop \n" \
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@ -102,8 +102,8 @@ static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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return result; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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#define ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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static __inline__ type pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
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{ \
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int temp, result; \
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\
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@ -120,10 +120,10 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_fetch_" #op " \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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"1: " #ll " %1, %2 # " #pfx "_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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" " #sc " %0, %2 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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" .set pop \n" \
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" move %0, %1 \n" \
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@ -134,32 +134,50 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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return result; \
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}
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
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ATOMIC_OPS(add, +=, addu)
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ATOMIC_OPS(sub, -=, subu)
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ATOMIC_OPS(atomic, add, int, +=, addu, ll, sc)
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ATOMIC_OPS(atomic, sub, int, -=, subu, ll, sc)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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#ifdef CONFIG_64BIT
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ATOMIC_OPS(atomic64, add, s64, +=, daddu, lld, scd)
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ATOMIC_OPS(atomic64, sub, s64, -=, dsubu, lld, scd)
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# define atomic64_add_return_relaxed atomic64_add_return_relaxed
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# define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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# define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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# define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#endif /* CONFIG_64BIT */
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, xor)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
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ATOMIC_OPS(atomic, and, int, &=, and, ll, sc)
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ATOMIC_OPS(atomic, or, int, |=, or, ll, sc)
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ATOMIC_OPS(atomic, xor, int, ^=, xor, ll, sc)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#ifdef CONFIG_64BIT
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ATOMIC_OPS(atomic64, and, s64, &=, and, lld, scd)
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ATOMIC_OPS(atomic64, or, s64, |=, or, lld, scd)
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ATOMIC_OPS(atomic64, xor, s64, ^=, xor, lld, scd)
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# define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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# define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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# define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#endif
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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@ -243,130 +261,6 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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*/
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#define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC64_OP(op, c_op, asm_op) \
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static __inline__ void atomic64_##op(s64 i, atomic64_t * v) \
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{ \
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if (kernel_uses_llsc) { \
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s64 temp; \
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\
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loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %0, %1 # atomic64_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" scd %0, %1 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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" .set pop \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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}
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#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
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static __inline__ s64 atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \
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{ \
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s64 result; \
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\
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if (kernel_uses_llsc) { \
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s64 temp; \
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\
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loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set pop \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result c_op i; \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
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static __inline__ s64 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \
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{ \
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s64 result; \
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\
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if (kernel_uses_llsc) { \
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s64 temp; \
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\
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loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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" move %0, %1 \n" \
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" .set pop \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC64_OPS(op, c_op, asm_op) \
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ATOMIC64_OP(op, c_op, asm_op) \
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ATOMIC64_OP_RETURN(op, c_op, asm_op) \
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ATOMIC64_FETCH_OP(op, c_op, asm_op)
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ATOMIC64_OPS(add, +=, daddu)
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ATOMIC64_OPS(sub, -=, dsubu)
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, c_op, asm_op) \
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ATOMIC64_OP(op, c_op, asm_op) \
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ATOMIC64_FETCH_OP(op, c_op, asm_op)
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ATOMIC64_OPS(and, &=, and)
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ATOMIC64_OPS(or, |=, or)
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ATOMIC64_OPS(xor, ^=, xor)
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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/*
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* atomic64_sub_if_positive - conditionally subtract integer from atomic
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* variable
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