MIPS: Prevent unaligned accesses during stack unwinding
During stack unwinding we call a number of functions to determine what
type of instruction we're looking at. The union mips_instruction pointer
provided to them may be pointing at a 2 byte, but not 4 byte, aligned
address & we thus cannot directly access the 4 byte wide members of the
union mips_instruction. To avoid this is_ra_save_ins() copies the
required half-words of the microMIPS instruction to a correctly aligned
union mips_instruction on the stack, which it can then access safely.
The is_jump_ins() & is_sp_move_ins() functions do not correctly perform
this temporary copy, and instead attempt to directly dereference 4 byte
fields which may be misaligned and lead to an address exception.
Fix this by copying the instruction halfwords to a temporary union
mips_instruction in get_frame_info() such that we can provide a 4 byte
aligned union mips_instruction to the is_*_ins() functions and they do
not need to deal with misalignment themselves.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 34c2f668d0
("MIPS: microMIPS: Add unaligned access support.")
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14529/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
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@ -199,8 +199,6 @@ struct mips_frame_info {
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static inline int is_ra_save_ins(union mips_instruction *ip)
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static inline int is_ra_save_ins(union mips_instruction *ip)
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{
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{
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#ifdef CONFIG_CPU_MICROMIPS
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#ifdef CONFIG_CPU_MICROMIPS
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union mips_instruction mmi;
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/*
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/*
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* swsp ra,offset
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* swsp ra,offset
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* swm16 reglist,offset(sp)
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* swm16 reglist,offset(sp)
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@ -210,23 +208,20 @@ static inline int is_ra_save_ins(union mips_instruction *ip)
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*
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*
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* microMIPS is way more fun...
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* microMIPS is way more fun...
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*/
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*/
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if (mm_insn_16bit(ip->halfword[0])) {
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if (mm_insn_16bit(ip->halfword[1])) {
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mmi.word = (ip->halfword[0] << 16);
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return (ip->mm16_r5_format.opcode == mm_swsp16_op &&
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return (mmi.mm16_r5_format.opcode == mm_swsp16_op &&
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ip->mm16_r5_format.rt == 31) ||
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mmi.mm16_r5_format.rt == 31) ||
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(ip->mm16_m_format.opcode == mm_pool16c_op &&
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(mmi.mm16_m_format.opcode == mm_pool16c_op &&
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ip->mm16_m_format.func == mm_swm16_op);
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mmi.mm16_m_format.func == mm_swm16_op);
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}
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}
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else {
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else {
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mmi.halfword[0] = ip->halfword[1];
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return (ip->mm_m_format.opcode == mm_pool32b_op &&
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mmi.halfword[1] = ip->halfword[0];
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ip->mm_m_format.rd > 9 &&
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return (mmi.mm_m_format.opcode == mm_pool32b_op &&
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ip->mm_m_format.base == 29 &&
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mmi.mm_m_format.rd > 9 &&
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ip->mm_m_format.func == mm_swm32_func) ||
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mmi.mm_m_format.base == 29 &&
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(ip->i_format.opcode == mm_sw32_op &&
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mmi.mm_m_format.func == mm_swm32_func) ||
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ip->i_format.rs == 29 &&
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(mmi.i_format.opcode == mm_sw32_op &&
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ip->i_format.rt == 31);
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mmi.i_format.rs == 29 &&
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mmi.i_format.rt == 31);
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}
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}
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#else
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#else
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/* sw / sd $ra, offset($sp) */
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/* sw / sd $ra, offset($sp) */
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@ -247,12 +242,8 @@ static inline int is_jump_ins(union mips_instruction *ip)
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*
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*
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* microMIPS is kind of more fun...
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* microMIPS is kind of more fun...
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*/
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*/
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union mips_instruction mmi;
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if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
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(ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) ||
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mmi.word = (ip->halfword[0] << 16);
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if ((mmi.mm16_r5_format.opcode == mm_pool16c_op &&
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(mmi.mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) ||
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ip->j_format.opcode == mm_jal32_op)
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ip->j_format.opcode == mm_jal32_op)
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return 1;
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return 1;
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if (ip->r_format.opcode != mm_pool32a_op ||
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if (ip->r_format.opcode != mm_pool32a_op ||
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@ -281,15 +272,13 @@ static inline int is_sp_move_ins(union mips_instruction *ip)
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*
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*
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* microMIPS is not more fun...
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* microMIPS is not more fun...
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*/
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*/
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if (mm_insn_16bit(ip->halfword[0])) {
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if (mm_insn_16bit(ip->halfword[1])) {
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union mips_instruction mmi;
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return (ip->mm16_r3_format.opcode == mm_pool16d_op &&
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ip->mm16_r3_format.simmediate && mm_addiusp_func) ||
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mmi.word = (ip->halfword[0] << 16);
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(ip->mm16_r5_format.opcode == mm_pool16d_op &&
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return (mmi.mm16_r3_format.opcode == mm_pool16d_op &&
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ip->mm16_r5_format.rt == 29);
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mmi.mm16_r3_format.simmediate && mm_addiusp_func) ||
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(mmi.mm16_r5_format.opcode == mm_pool16d_op &&
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mmi.mm16_r5_format.rt == 29);
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}
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}
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return ip->mm_i_format.opcode == mm_addiu32_op &&
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return ip->mm_i_format.opcode == mm_addiu32_op &&
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ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29;
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ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29;
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#else
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#else
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@ -304,7 +293,8 @@ static inline int is_sp_move_ins(union mips_instruction *ip)
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static int get_frame_info(struct mips_frame_info *info)
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static int get_frame_info(struct mips_frame_info *info)
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{
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{
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union mips_instruction *ip;
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bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
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union mips_instruction insn, *ip;
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unsigned max_insns = info->func_size / sizeof(union mips_instruction);
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unsigned max_insns = info->func_size / sizeof(union mips_instruction);
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unsigned i;
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unsigned i;
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@ -320,11 +310,21 @@ static int get_frame_info(struct mips_frame_info *info)
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max_insns = min(128U, max_insns);
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max_insns = min(128U, max_insns);
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for (i = 0; i < max_insns; i++, ip++) {
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for (i = 0; i < max_insns; i++, ip++) {
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if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
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insn.halfword[0] = 0;
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insn.halfword[1] = ip->halfword[0];
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} else if (is_mmips) {
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insn.halfword[0] = ip->halfword[1];
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insn.halfword[1] = ip->halfword[0];
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} else {
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insn.word = ip->word;
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}
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if (is_jump_ins(ip))
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if (is_jump_ins(&insn))
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break;
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break;
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if (!info->frame_size) {
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if (!info->frame_size) {
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if (is_sp_move_ins(ip))
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if (is_sp_move_ins(&insn))
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{
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{
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#ifdef CONFIG_CPU_MICROMIPS
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#ifdef CONFIG_CPU_MICROMIPS
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if (mm_insn_16bit(ip->halfword[0]))
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if (mm_insn_16bit(ip->halfword[0]))
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@ -347,7 +347,7 @@ static int get_frame_info(struct mips_frame_info *info)
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}
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}
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continue;
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continue;
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}
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}
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if (info->pc_offset == -1 && is_ra_save_ins(ip)) {
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if (info->pc_offset == -1 && is_ra_save_ins(&insn)) {
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info->pc_offset =
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info->pc_offset =
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ip->i_format.simmediate / sizeof(long);
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ip->i_format.simmediate / sizeof(long);
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break;
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break;
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