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powerpc/8xx: Use SPRN_SPRG_SCRATCH2 in ITLB miss exception 

In order to re-enable MMU earlier, ensure ITLB miss exception
cannot clobber SPRN_SPRG_SCRATCH0 and SPRN_SPRG_SCRATCH1.
Do so by using SPRN_SPRG_SCRATCH2 and SPRN_M_TW instead, like
the DTLB miss exception.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/abc78e8e9577d473691ebb9996c6413b37bfd9ca.1606231483.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy 2020-11-24 15:24:57 +00:00 committed by Michael Ellerman
parent 576e02bbf1
commit a314ea5abf
2 changed files with 8 additions and 8 deletions
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12
arch/powerpc/kernel/head_8xx.S
View File

@ -190,8 +190,8 @@ SystemCall:
#endif #endif
InstructionTLBMiss: InstructionTLBMiss:
mtspr SPRN_SPRG_SCRATCH0, r10 mtspr SPRN_SPRG_SCRATCH2, r10
mtspr SPRN_SPRG_SCRATCH1, r11 mtspr SPRN_M_TW, r11
/* If we are faulting a kernel address, we have to use the /* If we are faulting a kernel address, we have to use the
* kernel page tables. * kernel page tables.
@ -230,8 +230,8 @@ InstructionTLBMiss:
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
/* Restore registers */ /* Restore registers */
0: mfspr r10, SPRN_SPRG_SCRATCH0 0: mfspr r10, SPRN_SPRG_SCRATCH2
mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r11, SPRN_M_TW
rfi rfi
patch_site 0b, patch__itlbmiss_exit_1 patch_site 0b, patch__itlbmiss_exit_1
@ -240,8 +240,8 @@ InstructionTLBMiss:
0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
addi r10, r10, 1 addi r10, r10, 1
stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r10, SPRN_SPRG_SCRATCH2
mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r11, SPRN_M_TW
rfi rfi
#endif #endif

4
arch/powerpc/perf/8xx-pmu.c
View File

@ -165,9 +165,9 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags)
break; break;
case PERF_8xx_ID_ITLB_LOAD_MISS: case PERF_8xx_ID_ITLB_LOAD_MISS:
if (atomic_dec_return(&itlb_miss_ref) == 0) { if (atomic_dec_return(&itlb_miss_ref) == 0) {
/* mfspr r10, SPRN_SPRG_SCRATCH0 */ /* mfspr r10, SPRN_SPRG_SCRATCH2 */
struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) | struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
__PPC_SPR(SPRN_SPRG_SCRATCH0)); __PPC_SPR(SPRN_SPRG_SCRATCH2));
patch_instruction_site(&patch__itlbmiss_exit_1, insn); patch_instruction_site(&patch__itlbmiss_exit_1, insn);
} }