[SCSI] lpfc 8.1.7 : Fix failing firmware download due to mailbox delays needing to be longer
Fix failing firmware download due to mailbox delays needing to be longer. Signed-off-by: James Smart <James.Smart@emulex.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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@ -1000,7 +1000,8 @@ sysfs_mbox_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
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spin_unlock_irq(phba->host->host_lock);
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rc = lpfc_sli_issue_mbox_wait (phba,
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phba->sysfs_mbox.mbox,
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phba->fc_ratov * 2);
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lpfc_mbox_tmo_val(phba,
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phba->sysfs_mbox.mbox->mb.mbxCommand) * HZ);
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spin_lock_irq(phba->host->host_lock);
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}
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@ -127,6 +127,7 @@ void lpfc_config_port(struct lpfc_hba *, LPFC_MBOXQ_t *);
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void lpfc_kill_board(struct lpfc_hba *, LPFC_MBOXQ_t *);
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void lpfc_mbox_put(struct lpfc_hba *, LPFC_MBOXQ_t *);
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LPFC_MBOXQ_t *lpfc_mbox_get(struct lpfc_hba *);
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int lpfc_mbox_tmo_val(struct lpfc_hba *, int);
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int lpfc_mem_alloc(struct lpfc_hba *);
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void lpfc_mem_free(struct lpfc_hba *);
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@ -651,3 +651,19 @@ lpfc_mbox_get(struct lpfc_hba * phba)
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return mbq;
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}
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int
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lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd)
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{
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switch (cmd) {
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case MBX_WRITE_NV: /* 0x03 */
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case MBX_UPDATE_CFG: /* 0x1B */
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case MBX_DOWN_LOAD: /* 0x1C */
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case MBX_DEL_LD_ENTRY: /* 0x1D */
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case MBX_LOAD_AREA: /* 0x81 */
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case MBX_FLASH_WR_ULA: /* 0x98 */
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case MBX_LOAD_EXP_ROM: /* 0x9C */
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return LPFC_MBOX_TMO_FLASH_CMD;
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}
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return LPFC_MBOX_TMO;
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}
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@ -2197,7 +2197,8 @@ lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
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return (MBX_NOT_FINISHED);
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}
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/* timeout active mbox command */
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mod_timer(&psli->mbox_tmo, jiffies + HZ * LPFC_MBOX_TMO);
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mod_timer(&psli->mbox_tmo, (jiffies +
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(HZ * lpfc_mbox_tmo_val(phba, mb->mbxCommand))));
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}
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/* Mailbox cmd <cmd> issue */
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@ -2257,7 +2258,6 @@ lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
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break;
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case MBX_POLL:
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i = 0;
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psli->mbox_active = NULL;
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if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
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/* First read mbox status word */
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@ -2271,11 +2271,14 @@ lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
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/* Read the HBA Host Attention Register */
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ha_copy = readl(phba->HAregaddr);
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i = lpfc_mbox_tmo_val(phba, mb->mbxCommand);
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i *= 1000; /* Convert to ms */
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/* Wait for command to complete */
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while (((word0 & OWN_CHIP) == OWN_CHIP) ||
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(!(ha_copy & HA_MBATT) &&
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(phba->hba_state > LPFC_WARM_START))) {
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if (i++ >= 100) {
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if (i-- <= 0) {
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psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
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spin_unlock_irqrestore(phba->host->host_lock,
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drvr_flag);
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@ -2293,7 +2296,7 @@ lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
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/* Can be in interrupt context, do not sleep */
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/* (or might be called with interrupts disabled) */
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mdelay(i);
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mdelay(1);
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spin_lock_irqsave(phba->host->host_lock, drvr_flag);
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@ -225,3 +225,9 @@ struct lpfc_sli {
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#define LPFC_MBOX_TMO 30 /* Sec tmo for outstanding mbox
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command */
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#define LPFC_MBOX_TMO_FLASH_CMD 300 /* Sec tmo for outstanding FLASH write
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* or erase cmds. This is especially
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* long because of the potential of
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* multiple flash erases that can be
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* spawned.
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*/
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