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linux-sg2042
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qed*: Refactoring and rearranging FW API with no functional impact 

This patch refactors and reorders the FW API files in preparation of
upgrading the code to support new FW.

- Make use of the BIT macro in appropriate places.
- Whitespace changes to align values and code blocks.
- Comments are updated (spelling mistakes, removed if not clear).
- Group together code blocks which are related or deal with similar
 matters.

Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com>
Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com>
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tomer Tayar 2017-12-27 19:30:05 +02:00 committed by David S. Miller
parent bbb6189df4
commit a2e7699eb5
20 changed files with 6535 additions and 6094 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
View File

@ -494,7 +494,7 @@ struct rdma_sq_fmr_wqe {
#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT 6
#define RDMA_SQ_FMR_WQE_RESERVED4_MASK 0x1FF
#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 7
__le32 Reserved5;
__le32 reserved5;
};
/* First element (16 bytes) of fmr wqe */
@ -574,7 +574,7 @@ struct rdma_sq_fmr_wqe_3rd {
#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT 6
#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK 0x1FF
#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT 7
__le32 Reserved5;
__le32 reserved5;
};
struct rdma_sq_local_inv_wqe {

4
drivers/net/ethernet/qlogic/qed/qed_cxt.c
View File

@ -110,7 +110,7 @@ struct src_ent {
};
#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
#define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12)
#define CONN_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
@ -2326,7 +2326,7 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
elem = (union type1_task_context *)elem_start;
SET_FIELD(elem->roce_ctx.tdif_context.flags1,
TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);
elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
}
}

102
drivers/net/ethernet/qlogic/qed/qed_debug.c
View File

@ -358,20 +358,14 @@ struct phy_defs {
(arr)[i] = qed_rd(dev, ptt, addr); \
} while (0)
#ifndef DWORDS_TO_BYTES
#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD)
#endif
#ifndef BYTES_TO_DWORDS
#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
#endif
/* extra lines include a signature line + optional latency events line */
#ifndef NUM_DBG_LINES
/* Extra lines include a signature line + optional latency events line */
#define NUM_EXTRA_DBG_LINES(block_desc) \
(1 + ((block_desc)->has_latency_events ? 1 : 0))
#define NUM_DBG_LINES(block_desc) \
((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
#endif
#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2)
#define RAM_LINES_TO_BYTES(lines) \
@ -441,23 +435,17 @@ struct phy_defs {
#define FW_IMG_MAIN 1
#ifndef REG_FIFO_ELEMENT_DWORDS
#define REG_FIFO_ELEMENT_DWORDS 2
#endif
#define REG_FIFO_DEPTH_ELEMENTS 32
#define REG_FIFO_DEPTH_DWORDS \
(REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)
#ifndef IGU_FIFO_ELEMENT_DWORDS
#define IGU_FIFO_ELEMENT_DWORDS 4
#endif
#define IGU_FIFO_DEPTH_ELEMENTS 64
#define IGU_FIFO_DEPTH_DWORDS \
(IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)
#ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS
#define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2
#endif
#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20
#define PROTECTION_OVERRIDE_DEPTH_DWORDS \
(PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \
@ -1089,6 +1077,20 @@ static struct block_defs block_xyld_defs = {
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12
};
static struct block_defs block_ptld_defs = {
"ptld", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_ypld_defs = {
"ypld", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_prm_defs = {
"prm",
{true, true}, false, 0,
@ -1221,6 +1223,34 @@ static struct block_defs block_cau_defs = {
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19
};
static struct block_defs block_rgfs_defs = {
"rgfs", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_rgsrc_defs = {
"rgsrc", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_tgfs_defs = {
"tgfs", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_tgsrc_defs = {
"tgsrc", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_umac_defs = {
"umac",
{false, true}, false, 0,
@ -1338,48 +1368,6 @@ static struct block_defs block_avs_wrap_defs = {
true, false, DBG_RESET_REG_MISCS_PL_UA, 11
};
static struct block_defs block_rgfs_defs = {
"rgfs", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_rgsrc_defs = {
"rgsrc", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_tgfs_defs = {
"tgfs", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_tgsrc_defs = {
"tgsrc", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_ptld_defs = {
"ptld", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_ypld_defs = {
"ypld", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_misc_aeu_defs = {
"misc_aeu", {false, false}, false, 0,
{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
@ -5596,10 +5584,6 @@ struct igu_fifo_addr_data {
#define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4
/********************************* Macros ************************************/
#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
/***************************** Constant Arrays *******************************/
struct user_dbg_array {

4
drivers/net/ethernet/qlogic/qed/qed_dev.c
View File

@ -758,7 +758,7 @@ static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
/* This function reconfigures the QM pf on the fly.
* For this purpose we:
* 1. reconfigure the QM database
* 2. set new values to runtime arrat
* 2. set new values to runtime array
* 3. send an sdm_qm_cmd through the rbc interface to stop the QM
* 4. activate init tool in QM_PF stage
* 5. send an sdm_qm_cmd through rbc interface to release the QM
@ -1515,7 +1515,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
}
/* Protocl Configuration */
/* Protocol Configuration */
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
(p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,

1397
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View File

File diff suppressed because it is too large Load Diff

70
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
View File

@ -47,50 +47,87 @@
#define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \
0x100) - 1 : 0)
#define QM_INVALID_PQ_ID 0xffff
/* Feature enable */
#define QM_BYPASS_EN 1
#define QM_BYTE_CRD_EN 1
/* Other PQ constants */
#define QM_OTHER_PQS_PER_PF 4
/* WFQ constants */
/* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
#define QM_WFQ_UPPER_BOUND 62500000
/* Bit of VOQ in WFQ VP PQ map */
#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
/* Bit of PF in WFQ VP PQ map */
#define QM_WFQ_VP_PQ_PF_SHIFT 5
/* 0x9000 = 4*9*1024 */
#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
/* Max WFQ increment value is 0.7 * upper bound */
#define QM_WFQ_MAX_INC_VAL 43750000
/* RL constants */
#define QM_RL_UPPER_BOUND 62500000
#define QM_RL_PERIOD 5 /* in us */
/* Period in us */
#define QM_RL_PERIOD 5
/* Period in 25MHz cycles */
#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
#define QM_RL_MAX_INC_VAL 43750000
/* RL increment value - rate is specified in mbps */
#define QM_RL_INC_VAL(rate) max_t(u32, \
(u32)(((rate ? rate : \
1000000) * \
QM_RL_PERIOD * \
101) / (8 * 100)), 1)
/* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
#define QM_RL_UPPER_BOUND 62500000
/* Max PF RL increment value is 0.7 * upper bound */
#define QM_RL_MAX_INC_VAL 43750000
/* AFullOprtnstcCrdMask constants */
#define QM_OPPOR_LINE_VOQ_DEF 1
#define QM_OPPOR_FW_STOP_DEF 0
#define QM_OPPOR_PQ_EMPTY_DEF 1
/* Command Queue constants */
/* Pure LB CmdQ lines (+spare) */
#define PBF_CMDQ_PURE_LB_LINES 150
#define PBF_CMDQ_LINES_RT_OFFSET(voq) ( \
PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * \
(PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
#define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
(PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
(ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
#define PBF_BTB_GUARANTEED_RT_OFFSET(voq) ( \
PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * \
(PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
#define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
(PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
(ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
#define QM_VOQ_LINE_CRD(pbf_cmd_lines) ((((pbf_cmd_lines) - \
4) * \
2) | QM_LINE_CRD_REG_SIGN_BIT)
#define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
/* BTB: blocks constants (block size = 256B) */
/* 256B blocks in 9700B packet */
#define BTB_JUMBO_PKT_BLOCKS 38
/* Headroom per-port */
#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
#define BTB_PURE_LB_FACTOR 10
/* Factored (hence really 0.7) */
#define BTB_PURE_LB_RATIO 7
/* QM stop command constants */
#define QM_STOP_PQ_MASK_WIDTH 32
#define QM_STOP_CMD_ADDR 2
@ -108,11 +145,9 @@
#define QM_STOP_CMD_POLL_PERIOD_US 500
/* QM command macros */
#define QM_CMD_STRUCT_SIZE(cmd) cmd ## \
_STRUCT_SIZE
#define QM_CMD_SET_FIELD(var, cmd, field, \
value) SET_FIELD(var[cmd ## _ ## field ## \
_OFFSET], \
#define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE
#define QM_CMD_SET_FIELD(var, cmd, field, value) \
SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \
cmd ## _ ## field, \
value)
/* QM: VOQ macros */
@ -128,6 +163,7 @@
max_phy_tcs_pr_port) \
: LB_VOQ(port))
/******************** INTERNAL IMPLEMENTATION *********************/
/* Prepare PF RL enable/disable runtime init values */
static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
{

2
drivers/net/ethernet/qlogic/qed/qed_int.c
View File

@ -82,7 +82,7 @@ struct aeu_invert_reg_bit {
#define ATTENTION_LENGTH_SHIFT (4)
#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
ATTENTION_LENGTH_SHIFT)
#define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
#define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
ATTENTION_PARITY)

36
drivers/net/ethernet/qlogic/qed/qed_iscsi.c
View File

@ -62,22 +62,6 @@
#include "qed_sriov.h"
#include "qed_reg_addr.h"
static int
qed_iscsi_async_event(struct qed_hwfn *p_hwfn,
u8 fw_event_code,
u16 echo, union event_ring_data *data, u8 fw_return_code)
{
if (p_hwfn->p_iscsi_info->event_cb) {
struct qed_iscsi_info *p_iscsi = p_hwfn->p_iscsi_info;
return p_iscsi->event_cb(p_iscsi->event_context,
fw_event_code, data);
} else {
DP_NOTICE(p_hwfn, "iSCSI async completion is not set\n");
return -EINVAL;
}
}
struct qed_iscsi_conn {
struct list_head list_entry;
bool free_on_delete;
@ -161,6 +145,22 @@ struct qed_iscsi_conn {
u8 abortive_dsconnect;
};
static int
qed_iscsi_async_event(struct qed_hwfn *p_hwfn,
u8 fw_event_code,
u16 echo, union event_ring_data *data, u8 fw_return_code)
{
if (p_hwfn->p_iscsi_info->event_cb) {
struct qed_iscsi_info *p_iscsi = p_hwfn->p_iscsi_info;
return p_iscsi->event_cb(p_iscsi->event_context,
fw_event_code, data);
} else {
DP_NOTICE(p_hwfn, "iSCSI async completion is not set\n");
return -EINVAL;
}
}
static int
qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn,
enum spq_mode comp_mode,
@ -276,7 +276,7 @@ qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn,
p_ramrod->tcp_init.two_msl_timer = cpu_to_le32(p_params->two_msl_timer);
val = p_params->tx_sws_timer;
p_ramrod->tcp_init.tx_sws_timer = cpu_to_le16(val);
p_ramrod->tcp_init.maxfinrt = p_params->max_fin_rt;
p_ramrod->tcp_init.max_fin_rt = p_params->max_fin_rt;
p_hwfn->p_iscsi_info->event_context = event_context;
p_hwfn->p_iscsi_info->event_cb = async_event_cb;
@ -304,8 +304,8 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
int rc = 0;
u32 dval;
u16 wval;
u8 i;
u16 *p;
u8 i;
/* Get SPQ entry */
memset(&init_data, 0, sizeof(init_data));

77
drivers/scsi/qedi/qedi_fw_api.c
View File

@ -342,56 +342,57 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
cpu_to_le16(dif_task_params->application_tag_mask);
SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_CRC_SEED,
dif_task_params->crc_seed ? 1 : 0);
SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_HOSTGUARDTYPE,
SET_FIELD(rdif_context->flags0,
RDIF_TASK_CONTEXT_HOST_GUARD_TYPE,
dif_task_params->host_guard_type);
SET_FIELD(rdif_context->flags0,
RDIF_TASK_CONTEXT_PROTECTIONTYPE,
RDIF_TASK_CONTEXT_PROTECTION_TYPE,
dif_task_params->protection_type);
SET_FIELD(rdif_context->flags0,
RDIF_TASK_CONTEXT_INITIALREFTAGVALID, 1);
RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID, 1);
SET_FIELD(rdif_context->flags0,
RDIF_TASK_CONTEXT_KEEPREFTAGCONST,
RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST,
dif_task_params->keep_ref_tag_const ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_VALIDATEAPPTAG,
RDIF_TASK_CONTEXT_VALIDATE_APP_TAG,
(dif_task_params->validate_app_tag &&
dif_task_params->dif_on_network) ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_VALIDATEGUARD,
RDIF_TASK_CONTEXT_VALIDATE_GUARD,
(dif_task_params->validate_guard &&
dif_task_params->dif_on_network) ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_VALIDATEREFTAG,
RDIF_TASK_CONTEXT_VALIDATE_REF_TAG,
(dif_task_params->validate_ref_tag &&
dif_task_params->dif_on_network) ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_HOSTINTERFACE,
RDIF_TASK_CONTEXT_HOST_INTERFACE,
dif_task_params->dif_on_host ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_NETWORKINTERFACE,
RDIF_TASK_CONTEXT_NETWORK_INTERFACE,
dif_task_params->dif_on_network ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_FORWARDGUARD,
RDIF_TASK_CONTEXT_FORWARD_GUARD,
dif_task_params->forward_guard ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_FORWARDAPPTAG,
RDIF_TASK_CONTEXT_FORWARD_APP_TAG,
dif_task_params->forward_app_tag ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_FORWARDREFTAG,
RDIF_TASK_CONTEXT_FORWARD_REF_TAG,
dif_task_params->forward_ref_tag ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK,
RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK,
dif_task_params->forward_app_tag_with_mask ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK,
RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK,
dif_task_params->forward_ref_tag_with_mask ? 1 : 0);
SET_FIELD(rdif_context->flags1,
RDIF_TASK_CONTEXT_INTERVALSIZE,
RDIF_TASK_CONTEXT_INTERVAL_SIZE,
dif_task_params->dif_block_size_log - 9);
SET_FIELD(rdif_context->state,
RDIF_TASK_CONTEXT_REFTAGMASK,
RDIF_TASK_CONTEXT_REF_TAG_MASK,
dif_task_params->ref_tag_mask);
SET_FIELD(rdif_context->state, RDIF_TASK_CONTEXT_IGNOREAPPTAG,
SET_FIELD(rdif_context->state, RDIF_TASK_CONTEXT_IGNORE_APP_TAG,
dif_task_params->ignore_app_tag);
}
@ -399,7 +400,7 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
task_type == ISCSI_TASK_TYPE_INITIATOR_WRITE) {
tdif_context->app_tag_value =
cpu_to_le16(dif_task_params->application_tag);
tdif_context->partial_crc_valueB =
tdif_context->partial_crc_value_b =
cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000);
tdif_context->partial_crc_value_a =
cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000);
@ -407,59 +408,63 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
dif_task_params->crc_seed ? 1 : 0);
SET_FIELD(tdif_context->flags0,
TDIF_TASK_CONTEXT_SETERRORWITHEOP,
TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP,
dif_task_params->tx_dif_conn_err_en ? 1 : 0);
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDGUARD,
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARD_GUARD,
dif_task_params->forward_guard ? 1 : 0);
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDAPPTAG,
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_FORWARD_APP_TAG,
dif_task_params->forward_app_tag ? 1 : 0);
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDREFTAG,
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_FORWARD_REF_TAG,
dif_task_params->forward_ref_tag ? 1 : 0);
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_INTERVALSIZE,
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_INTERVAL_SIZE,
dif_task_params->dif_block_size_log - 9);
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_HOSTINTERFACE,
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_HOST_INTERFACE,
dif_task_params->dif_on_host ? 1 : 0);
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_NETWORKINTERFACE,
TDIF_TASK_CONTEXT_NETWORK_INTERFACE,
dif_task_params->dif_on_network ? 1 : 0);
val = cpu_to_le32(dif_task_params->initial_ref_tag);
tdif_context->initial_ref_tag = val;
tdif_context->app_tag_mask =
cpu_to_le16(dif_task_params->application_tag_mask);
SET_FIELD(tdif_context->flags0,
TDIF_TASK_CONTEXT_HOSTGUARDTYPE,
TDIF_TASK_CONTEXT_HOST_GUARD_TYPE,
dif_task_params->host_guard_type);
SET_FIELD(tdif_context->flags0,
TDIF_TASK_CONTEXT_PROTECTIONTYPE,
TDIF_TASK_CONTEXT_PROTECTION_TYPE,
dif_task_params->protection_type);
SET_FIELD(tdif_context->flags0,
TDIF_TASK_CONTEXT_INITIALREFTAGVALID,
TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID,
dif_task_params->initial_ref_tag_is_valid ? 1 : 0);
SET_FIELD(tdif_context->flags0,
TDIF_TASK_CONTEXT_KEEPREFTAGCONST,
TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST,
dif_task_params->keep_ref_tag_const ? 1 : 0);
SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_VALIDATEGUARD,
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_VALIDATE_GUARD,
(dif_task_params->validate_guard &&
dif_task_params->dif_on_host) ? 1 : 0);
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_VALIDATEAPPTAG,
TDIF_TASK_CONTEXT_VALIDATE_APP_TAG,
(dif_task_params->validate_app_tag &&
dif_task_params->dif_on_host) ? 1 : 0);
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_VALIDATEREFTAG,
TDIF_TASK_CONTEXT_VALIDATE_REF_TAG,
(dif_task_params->validate_ref_tag &&
dif_task_params->dif_on_host) ? 1 : 0);
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK,
TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK,
dif_task_params->forward_app_tag_with_mask ? 1 : 0);
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK,
TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK,
dif_task_params->forward_ref_tag_with_mask ? 1 : 0);
SET_FIELD(tdif_context->flags1,
TDIF_TASK_CONTEXT_REFTAGMASK,
TDIF_TASK_CONTEXT_REF_TAG_MASK,
dif_task_params->ref_tag_mask);
SET_FIELD(tdif_context->flags0,
TDIF_TASK_CONTEXT_IGNOREAPPTAG,
TDIF_TASK_CONTEXT_IGNORE_APP_TAG,
dif_task_params->ignore_app_tag ? 1 : 0);
}
}

441
include/linux/qed/common_hsi.h
View File

@ -32,6 +32,7 @@
#ifndef _COMMON_HSI_H
#define _COMMON_HSI_H
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
@ -48,13 +49,19 @@
} while (0)
#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64)
#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
#define HILO_64(hi, lo) \
HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
#define HILO_64_REGPAIR(regpair) ({ \
typeof(regpair) __regpair = (regpair); \
HILO_64(__regpair.hi, __regpair.lo); })
#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
#ifndef __COMMON_HSI__
#define __COMMON_HSI__
/********************************/
/* PROTOCOL COMMON FW CONSTANTS */
/********************************/
#define X_FINAL_CLEANUP_AGG_INT 1
@ -147,9 +154,6 @@
#define LB_TC (NUM_OF_PHYS_TCS)
/* Num of possible traffic priority values */
#define NUM_OF_PRIO (8)
#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
@ -160,11 +164,6 @@
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
/* Clock values */
#define MASTER_CLK_FREQ_E4 (375e6)
#define STORM_CLK_FREQ_E4 (1000e6)
#define CLK25M_CLK_FREQ_E4 (25e6)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19
#define GTT_DWORD_SIZE_BITS 10
@ -201,7 +200,7 @@
#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
#define DQ_DEMS_ROCE_CQ_CONS 7
/* XCM agg val selection */
/* XCM agg val selection (HW) */
#define DQ_XCM_AGG_VAL_SEL_WORD2 0
#define DQ_XCM_AGG_VAL_SEL_WORD3 1
#define DQ_XCM_AGG_VAL_SEL_WORD4 2
@ -211,7 +210,7 @@
#define DQ_XCM_AGG_VAL_SEL_REG5 6
#define DQ_XCM_AGG_VAL_SEL_REG6 7
/* XCM agg val selection */
/* XCM agg val selection (FW) */
#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
@ -263,7 +262,7 @@
#define DQ_TCM_ROCE_RQ_PROD_CMD \
DQ_TCM_AGG_VAL_SEL_WORD0
/* XCM agg counter flag selection */
/* XCM agg counter flag selection (HW) */
#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
@ -273,7 +272,7 @@
#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
/* XCM agg counter flag selection */
/* XCM agg counter flag selection (FW) */
#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
@ -347,6 +346,7 @@
#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
#define DQ_REGION_SHIFT (12)
/* DPM */
@ -359,29 +359,30 @@
/* QM CONSTANTS */
/*****************/
/* number of TX queues in the QM */
/* Number of TX queues in the QM */
#define MAX_QM_TX_QUEUES_K2 512
#define MAX_QM_TX_QUEUES_BB 448
#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
/* number of Other queues in the QM */
/* Number of Other queues in the QM */
#define MAX_QM_OTHER_QUEUES_BB 64
#define MAX_QM_OTHER_QUEUES_K2 128
#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
/* number of queues in a PF queue group */
/* Number of queues in a PF queue group */
#define QM_PF_QUEUE_GROUP_SIZE 8
/* the size of a single queue element in bytes */
/* The size of a single queue element in bytes */
#define QM_PQ_ELEMENT_SIZE 4
/* base number of Tx PQs in the CM PQ representation.
* should be used when storing PQ IDs in CM PQ registers and context
/* Base number of Tx PQs in the CM PQ representation.
* Should be used when storing PQ IDs in CM PQ registers and context.
*/
#define CM_TX_PQ_BASE 0x200
/* number of global Vport/QCN rate limiters */
/* Number of global Vport/QCN rate limiters */
#define MAX_QM_GLOBAL_RLS 256
/* QM registers data */
#define QM_LINE_CRD_REG_WIDTH 16
#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
@ -432,8 +433,7 @@
#define IGU_CMD_INT_ACK_BASE 0x0400
#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
MAX_TOT_SB_PER_PATH - \
1)
MAX_TOT_SB_PER_PATH - 1)
#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
@ -447,8 +447,7 @@
#define IGU_CMD_PROD_UPD_BASE 0x0600
#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
MAX_TOT_SB_PER_PATH - \
1)
MAX_TOT_SB_PER_PATH - 1)
#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
/*****************/
@ -555,11 +554,6 @@
/* VF BAR */
#define PXP_VF_BAR0 0
#define PXP_VF_BAR0_START_GRC 0x3E00
#define PXP_VF_BAR0_GRC_LENGTH 0x200
#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
PXP_VF_BAR0_GRC_LENGTH - 1)
#define PXP_VF_BAR0_START_IGU 0
#define PXP_VF_BAR0_IGU_LENGTH 0x3000
#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
@ -577,40 +571,33 @@
#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \
+ \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- 1)
#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \
+ \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- 1)
#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \
+ \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- 1)
#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \
+ \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- 1)
#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \
+ \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- 1)
#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \
+ \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- 1)
#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \
PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_GRC 0x3E00
#define PXP_VF_BAR0_GRC_LENGTH 0x200
#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
PXP_VF_BAR0_GRC_LENGTH - 1)
#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
@ -624,11 +611,15 @@
#define PXP_NUM_ILT_RECORDS_BB 7600
#define PXP_NUM_ILT_RECORDS_K2 11000
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
/* Host Interface */
#define PXP_QUEUES_ZONE_MAX_NUM 320
/*****************/
/* PRM CONSTANTS */
/*****************/
#define PRM_DMA_PAD_BYTES_NUM 2
/*****************/
/* SDMs CONSTANTS */
/*****************/
@ -656,7 +647,7 @@
#define SDM_COMP_TYPE_INC_ORDER_CNT 9
/*****************/
/* PBF Constants */
/* PBF CONSTANTS */
/*****************/
/* Number of PBF command queue lines. Each line is 32B. */
@ -679,6 +670,7 @@ struct async_data {
u8 fw_debug_param;
};
/* Interrupt coalescing TimeSet */
struct coalescing_timeset {
u8 value;
#define COALESCING_TIMESET_TIMESET_MASK 0x7F
@ -692,20 +684,12 @@ struct common_queue_zone {
__le16 reserved;
};
/* ETH Rx producers data */
struct eth_rx_prod_data {
__le16 bd_prod;
__le16 cqe_prod;
};
struct regpair {
__le32 lo;
__le32 hi;
};
struct vf_pf_channel_eqe_data {
struct regpair msg_addr;
};
struct iscsi_eqe_data {
__le32 cid;
__le16 conn_id;
@ -719,52 +703,6 @@ struct iscsi_eqe_data {
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
struct rdma_eqe_destroy_qp {
__le32 cid;
u8 reserved[4];
};
union rdma_eqe_data {
struct regpair async_handle;
struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
};
struct malicious_vf_eqe_data {
u8 vf_id;
u8 err_id;
__le16 reserved[3];
};
struct initial_cleanup_eqe_data {
u8 vf_id;
u8 reserved[7];
};
/* Event Data Union */
union event_ring_data {
u8 bytes[8];
struct vf_pf_channel_eqe_data vf_pf_channel;
struct iscsi_eqe_data iscsi_info;
union rdma_eqe_data rdma_data;
struct malicious_vf_eqe_data malicious_vf;
struct initial_cleanup_eqe_data vf_init_cleanup;
};
/* Event Ring Entry */
struct event_ring_entry {
u8 protocol_id;
u8 opcode;
__le16 reserved0;
__le16 echo;
u8 fw_return_code;
u8 flags;
#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
union event_ring_data data;
};
/* Multi function mode */
enum mf_mode {
ERROR_MODE /* Unsupported mode */,
@ -781,13 +719,31 @@ enum protocol_type {
PROTOCOLID_CORE,
PROTOCOLID_ETH,
PROTOCOLID_IWARP,
PROTOCOLID_RESERVED5,
PROTOCOLID_RESERVED0,
PROTOCOLID_PREROCE,
PROTOCOLID_COMMON,
PROTOCOLID_RESERVED6,
PROTOCOLID_RESERVED1,
MAX_PROTOCOL_TYPE
};
struct regpair {
__le32 lo;
__le32 hi;
};
/* RoCE Destroy Event Data */
struct rdma_eqe_destroy_qp {
__le32 cid;
u8 reserved[4];
};
/* RDMA Event Data Union */
union rdma_eqe_data {
struct regpair async_handle;
struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
};
/* Ustorm Queue Zone */
struct ustorm_eth_queue_zone {
struct coalescing_timeset int_coalescing_timeset;
u8 reserved[3];
@ -798,7 +754,7 @@ struct ustorm_queue_zone {
struct common_queue_zone common;
};
/* status block structure */
/* Status block structure */
struct cau_pi_entry {
u32 prod;
#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
@ -811,7 +767,7 @@ struct cau_pi_entry {
#define CAU_PI_ENTRY_RESERVED_SHIFT 24
};
/* status block structure */
/* Status block structure */
struct cau_sb_entry {
u32 data;
#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
@ -839,7 +795,16 @@ struct cau_sb_entry {
#define CAU_SB_ENTRY_TPH_SHIFT 31
};
/* core doorbell data */
/* Igu cleanup bit values to distinguish between clean or producer consumer
* update.
*/
enum command_type_bit {
IGU_COMMAND_TYPE_NOP = 0,
IGU_COMMAND_TYPE_SET = 1,
MAX_COMMAND_TYPE_BIT
};
/* Core doorbell data */
struct core_db_data {
u8 params;
#define CORE_DB_DATA_DEST_MASK 0x3
@ -946,7 +911,7 @@ struct db_pwm_addr {
#define DB_PWM_ADDR_RESERVED1_SHIFT 28
};
/* Parameters to RoCE firmware, passed in EDPM doorbell */
/* Parameters to RDMA firmware, passed in EDPM doorbell */
struct db_rdma_dpm_params {
__le32 params;
#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
@ -969,7 +934,9 @@ struct db_rdma_dpm_params {
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
};
/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
/* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
* DPM burst.
*/
struct db_rdma_dpm_data {
__le16 icid;
__le16 prod_val;
@ -1044,6 +1011,7 @@ struct parsing_and_err_flags {
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
};
/* Parsing error flags bitmap */
struct parsing_err_flags {
__le16 flags;
#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
@ -1080,10 +1048,12 @@ struct parsing_err_flags {
#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
};
/* Pb context */
struct pb_context {
__le32 crc[4];
};
/* Concrete Function ID */
struct pxp_concrete_fid {
__le16 fid;
#define PXP_CONCRETE_FID_PFID_MASK 0xF
@ -1098,6 +1068,7 @@ struct pxp_concrete_fid {
#define PXP_CONCRETE_FID_VFID_SHIFT 8
};
/* Concrete Function ID */
struct pxp_pretend_concrete_fid {
__le16 fid;
#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
@ -1110,12 +1081,13 @@ struct pxp_pretend_concrete_fid {
#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
};
/* Function ID */
union pxp_pretend_fid {
struct pxp_pretend_concrete_fid concrete_fid;
__le16 opaque_fid;
};
/* Pxp Pretend Command Register. */
/* Pxp Pretend Command Register */
struct pxp_pretend_cmd {
union pxp_pretend_fid fid;
__le16 control;
@ -1139,7 +1111,7 @@ struct pxp_pretend_cmd {
#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
};
/* PTT Record in PXP Admin Window. */
/* PTT Record in PXP Admin Window */
struct pxp_ptt_entry {
__le32 offset;
#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
@ -1149,7 +1121,7 @@ struct pxp_ptt_entry {
struct pxp_pretend_cmd pretend;
};
/* VF Zone A Permission Register. */
/* VF Zone A Permission Register */
struct pxp_vf_zone_a_permission {
__le32 control;
#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
@ -1162,86 +1134,74 @@ struct pxp_vf_zone_a_permission {
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
};
/* RSS hash type */
/* Rdif context */
struct rdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
u8 flags0;
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
u8 partial_dif_data[7];
__le16 partial_crc_value;
__le16 partial_checksum_value;
__le32 offset_in_io;
__le16 flags1;
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
__le16 state;
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
__le32 reserved2;
};
/* RSS hash type */
enum rss_hash_type {
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
RSS_HASH_TYPE_TCP_IPV4 = 2,
RSS_HASH_TYPE_IPV6 = 3,
RSS_HASH_TYPE_TCP_IPV6 = 4,
RSS_HASH_TYPE_UDP_IPV4 = 5,
RSS_HASH_TYPE_UDP_IPV6 = 6,
MAX_RSS_HASH_TYPE
};
/* status block structure */
/* Status block structure */
struct status_block {
__le16 pi_array[PIS_PER_SB];
__le32 sb_num;
@ -1258,88 +1218,90 @@ struct status_block {
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
};
/* Tdif context */
struct tdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
__le16 partial_crc_valueB;
__le16 partial_checksum_valueB;
__le16 partial_crc_value_b;
__le16 partial_checksum_value_b;
__le16 stateB;
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
u8 reserved1;
u8 flags0;
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
__le32 flags1;
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
__le32 offset_in_iob;
__le32 offset_in_io_b;
__le16 partial_crc_value_a;
__le16 partial_checksum_valuea_;
__le32 offset_in_ioa;
__le16 partial_checksum_value_a;
__le32 offset_in_io_a;
u8 partial_dif_data_a[8];
u8 partial_dif_data_b[8];
};
/* Timers context */
struct timers_context {
__le32 logical_client_0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
@ -1385,6 +1347,7 @@ struct timers_context {
#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
};
/* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
enum tunnel_next_protocol {
e_unknown = 0,
e_l2 = 1,

43
include/linux/qed/eth_common.h
View File

@ -36,6 +36,7 @@
/********************/
/* ETH FW CONSTANTS */
/********************/
#define ETH_HSI_VER_MAJOR 3
#define ETH_HSI_VER_MINOR 10
@ -78,16 +79,16 @@
#define ETH_RX_MAX_BUFF_PER_PKT 5
#define ETH_RX_BD_THRESHOLD 12
/* num of MAC/VLAN filters */
/* Num of MAC/VLAN filters */
#define ETH_NUM_MAC_FILTERS 512
#define ETH_NUM_VLAN_FILTERS 512
/* approx. multicast constants */
/* Approx. multicast constants */
#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
#define ETH_MULTICAST_MAC_BINS 256
#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
/* ethernet vport update constants */
/* Ethernet vport update constants */
#define ETH_FILTER_RULES_COUNT 10
#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
#define ETH_RSS_KEY_SIZE_REGS 10
@ -123,7 +124,7 @@ struct eth_tx_1st_bd_flags {
#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
};
/* The parsing information data fo rthe first tx bd of a given packet. */
/* The parsing information data fo rthe first tx bd of a given packet */
struct eth_tx_data_1st_bd {
__le16 vlan;
u8 nbds;
@ -137,7 +138,7 @@ struct eth_tx_data_1st_bd {
#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
};
/* The parsing information data for the second tx bd of a given packet. */
/* The parsing information data for the second tx bd of a given packet */
struct eth_tx_data_2nd_bd {
__le16 tunn_ip_size;
__le16 bitfields1;
@ -168,7 +169,7 @@ struct eth_tx_data_2nd_bd {
#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
};
/* Firmware data for L2-EDPM packet. */
/* Firmware data for L2-EDPM packet */
struct eth_edpm_fw_data {
struct eth_tx_data_1st_bd data_1st_bd;
struct eth_tx_data_2nd_bd data_2nd_bd;
@ -179,7 +180,7 @@ struct eth_fast_path_cqe_fw_debug {
__le16 reserved2;
};
/* tunneling parsing flags */
/* Tunneling parsing flags */
struct eth_tunnel_parsing_flags {
u8 flags;
#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
@ -207,7 +208,7 @@ struct eth_pmd_flow_flags {
#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
};
/* Regular ETH Rx FP CQE. */
/* Regular ETH Rx FP CQE */
struct eth_fast_path_rx_reg_cqe {
u8 type;
u8 bitfields;
@ -231,7 +232,7 @@ struct eth_fast_path_rx_reg_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
/* TPA-continue ETH Rx FP CQE. */
/* TPA-continue ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_cont_cqe {
u8 type;
u8 tpa_agg_index;
@ -243,7 +244,7 @@ struct eth_fast_path_rx_tpa_cont_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
/* TPA-end ETH Rx FP CQE. */
/* TPA-end ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_end_cqe {
u8 type;
u8 tpa_agg_index;
@ -259,7 +260,7 @@ struct eth_fast_path_rx_tpa_end_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
/* TPA-start ETH Rx FP CQE. */
/* TPA-start ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_start_cqe {
u8 type;
u8 bitfields;
@ -295,7 +296,7 @@ struct eth_rx_bd {
struct regpair addr;
};
/* regular ETH Rx SP CQE */
/* Regular ETH Rx SP CQE */
struct eth_slow_path_rx_cqe {
u8 type;
u8 ramrod_cmd_id;
@ -306,7 +307,7 @@ struct eth_slow_path_rx_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
/* union for all ETH Rx CQE types */
/* Union for all ETH Rx CQE types */
union eth_rx_cqe {
struct eth_fast_path_rx_reg_cqe fast_path_regular;
struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
@ -366,7 +367,7 @@ struct eth_tx_2nd_bd {
struct eth_tx_data_2nd_bd data;
};
/* The parsing information data for the third tx bd of a given packet. */
/* The parsing information data for the third tx bd of a given packet */
struct eth_tx_data_3rd_bd {
__le16 lso_mss;
__le16 bitfields;
@ -389,7 +390,7 @@ struct eth_tx_3rd_bd {
struct eth_tx_data_3rd_bd data;
};
/* Complementary information for the regular tx bd of a given packet. */
/* Complementary information for the regular tx bd of a given packet */
struct eth_tx_data_bd {
__le16 reserved0;
__le16 bitfields;
@ -448,4 +449,16 @@ struct eth_db_data {
__le16 bd_prod;
};
/* RSS hash type */
enum rss_hash_type {
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
RSS_HASH_TYPE_TCP_IPV4 = 2,
RSS_HASH_TYPE_IPV6 = 3,
RSS_HASH_TYPE_TCP_IPV6 = 4,
RSS_HASH_TYPE_UDP_IPV4 = 5,
RSS_HASH_TYPE_UDP_IPV6 = 6,
MAX_RSS_HASH_TYPE
};
#endif /* __ETH_COMMON__ */

352
include/linux/qed/fcoe_common.h
View File

@ -8,172 +8,14 @@
#ifndef __FCOE_COMMON__
#define __FCOE_COMMON__
/*********************/
/* FCOE FW CONSTANTS */
/*********************/
#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
struct fcoe_abts_pkt {
__le32 abts_rsp_fc_payload_lo;
__le16 abts_rsp_rx_id;
u8 abts_rsp_rctl;
u8 reserved2;
};
/* FCoE additional WQE (Sq/XferQ) information */
union fcoe_additional_info_union {
__le32 previous_tid;
__le32 parent_tid;
__le32 burst_length;
__le32 seq_rec_updated_offset;
};
struct fcoe_exp_ro {
__le32 data_offset;
__le32 reserved;
};
union fcoe_cleanup_addr_exp_ro_union {
struct regpair abts_rsp_fc_payload_hi;
struct fcoe_exp_ro exp_ro;
};
/* FCoE Ramrod Command IDs */
enum fcoe_completion_status {
FCOE_COMPLETION_STATUS_SUCCESS,
FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
MAX_FCOE_COMPLETION_STATUS
};
struct fc_addr_nw {
u8 addr_lo;
u8 addr_mid;
u8 addr_hi;
};
/* FCoE connection offload */
struct fcoe_conn_offload_ramrod_data {
struct regpair sq_pbl_addr;
struct regpair sq_curr_page_addr;
struct regpair sq_next_page_addr;
struct regpair xferq_pbl_addr;
struct regpair xferq_curr_page_addr;
struct regpair xferq_next_page_addr;
struct regpair respq_pbl_addr;
struct regpair respq_curr_page_addr;
struct regpair respq_next_page_addr;
__le16 dst_mac_addr_lo;
__le16 dst_mac_addr_mid;
__le16 dst_mac_addr_hi;
__le16 src_mac_addr_lo;
__le16 src_mac_addr_mid;
__le16 src_mac_addr_hi;
__le16 tx_max_fc_pay_len;
__le16 e_d_tov_timer_val;
__le16 rx_max_fc_pay_len;
__le16 vlan_tag;
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
__le16 physical_q0;
__le16 rec_rr_tov_timer_val;
struct fc_addr_nw s_id;
u8 max_conc_seqs_c3;
struct fc_addr_nw d_id;
u8 flags;
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
__le16 conn_id;
u8 def_q_idx;
u8 reserved[5];
};
/* FCoE terminate connection request */
struct fcoe_conn_terminate_ramrod_data {
struct regpair terminate_params_addr;
};
struct fcoe_slow_sgl_ctx {
struct regpair base_sgl_addr;
__le16 curr_sge_off;
__le16 remainder_num_sges;
__le16 curr_sgl_index;
__le16 reserved;
};
union fcoe_dix_desc_ctx {
struct fcoe_slow_sgl_ctx dix_sgl;
struct scsi_sge cached_dix_sge;
};
struct fcoe_fast_sgl_ctx {
struct regpair sgl_start_addr;
__le32 sgl_byte_offset;
__le16 task_reuse_cnt;
__le16 init_offset_in_first_sge;
};
struct fcoe_fcp_cmd_payload {
__le32 opaque[8];
};
struct fcoe_fcp_rsp_payload {
__le32 opaque[6];
};
struct fcoe_fcp_xfer_payload {
__le32 opaque[3];
};
/* FCoE firmware function init */
struct fcoe_init_func_ramrod_data {
struct scsi_init_func_params func_params;
struct scsi_init_func_queues q_params;
__le16 mtu;
__le16 sq_num_pages_in_pbl;
__le32 reserved;
};
/* FCoE: Mode of the connection: Target or Initiator or both */
enum fcoe_mode_type {
FCOE_INITIATOR_MODE = 0x0,
FCOE_TARGET_MODE = 0x1,
FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
MAX_FCOE_MODE_TYPE
};
struct fcoe_rx_stat {
struct regpair fcoe_rx_byte_cnt;
struct regpair fcoe_rx_data_pkt_cnt;
struct regpair fcoe_rx_xfer_pkt_cnt;
struct regpair fcoe_rx_other_pkt_cnt;
__le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
__le32 fcoe_silent_drop_pkt_rq_full_cnt;
__le32 fcoe_silent_drop_pkt_crc_error_cnt;
__le32 fcoe_silent_drop_pkt_task_invalid_cnt;
__le32 fcoe_silent_drop_total_pkt_cnt;
__le32 rsrv;
};
struct fcoe_stat_ramrod_data {
struct regpair stat_params_addr;
};
/* The fcoe storm task context protection-information of Ystorm */
struct protection_info_ctx {
__le16 flags;
#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
@ -192,21 +34,40 @@ struct protection_info_ctx {
u8 dst_size;
};
/* The fcoe storm task context protection-information of Ystorm */
union protection_info_union_ctx {
struct protection_info_ctx info;
__le32 value;
};
/* FCP CMD payload */
struct fcoe_fcp_cmd_payload {
__le32 opaque[8];
};
/* FCP RSP payload */
struct fcoe_fcp_rsp_payload {
__le32 opaque[6];
};
/* FCP RSP payload */
struct fcp_rsp_payload_padded {
struct fcoe_fcp_rsp_payload rsp_payload;
__le32 reserved[2];
};
/* FCP RSP payload */
struct fcoe_fcp_xfer_payload {
__le32 opaque[3];
};
/* FCP RSP payload */
struct fcp_xfer_payload_padded {
struct fcoe_fcp_xfer_payload xfer_payload;
__le32 reserved[5];
};
/* Task params */
struct fcoe_tx_data_params {
__le32 data_offset;
__le32 offset_in_io;
@ -227,6 +88,7 @@ struct fcoe_tx_data_params {
__le16 reserved3;
};
/* Middle path parameters: FC header fields provided by the driver */
struct fcoe_tx_mid_path_params {
__le32 parameter;
u8 r_ctl;
@ -237,11 +99,13 @@ struct fcoe_tx_mid_path_params {
__le16 ox_id;
};
/* Task params */
struct fcoe_tx_params {
struct fcoe_tx_data_params data;
struct fcoe_tx_mid_path_params mid_path;
};
/* Union of FCP CMD payload \ TX params \ ABTS \ Cleanup */
union fcoe_tx_info_union_ctx {
struct fcoe_fcp_cmd_payload fcp_cmd_payload;
struct fcp_rsp_payload_padded fcp_rsp_payload;
@ -249,6 +113,22 @@ union fcoe_tx_info_union_ctx {
struct fcoe_tx_params tx_params;
};
/* Data sgl */
struct fcoe_slow_sgl_ctx {
struct regpair base_sgl_addr;
__le16 curr_sge_off;
__le16 remainder_num_sges;
__le16 curr_sgl_index;
__le16 reserved;
};
/* Union of DIX SGL \ cached DIX sges */
union fcoe_dix_desc_ctx {
struct fcoe_slow_sgl_ctx dix_sgl;
struct scsi_sge cached_dix_sge;
};
/* The fcoe storm task context of Ystorm */
struct ystorm_fcoe_task_st_ctx {
u8 task_type;
u8 sgl_mode;
@ -407,6 +287,27 @@ struct tstorm_fcoe_task_ag_ctx {
__le32 data_offset_next;
};
/* Cached data sges */
struct fcoe_exp_ro {
__le32 data_offset;
__le32 reserved;
};
/* Union of Cleanup address \ expected relative offsets */
union fcoe_cleanup_addr_exp_ro_union {
struct regpair abts_rsp_fc_payload_hi;
struct fcoe_exp_ro exp_ro;
};
/* Fields coppied from ABTSrsp pckt */
struct fcoe_abts_pkt {
__le32 abts_rsp_fc_payload_lo;
__le16 abts_rsp_rx_id;
u8 abts_rsp_rctl;
u8 reserved2;
};
/* FW read- write (modifyable) part The fcoe task storm context of Tstorm */
struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
__le16 flags;
@ -436,6 +337,7 @@ struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
__le16 reserved1;
};
/* FW read only part The fcoe task storm context of Tstorm */
struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
u8 task_type;
u8 dev_type;
@ -446,6 +348,7 @@ struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
__le32 rsrv;
};
/** The fcoe task storm context of Tstorm */
struct tstorm_fcoe_task_st_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
@ -507,6 +410,7 @@ struct mstorm_fcoe_task_ag_ctx {
__le32 reg2;
};
/* The fcoe task storm context of Mstorm */
struct mstorm_fcoe_task_st_ctx {
struct regpair rsp_buf_addr;
__le32 rsrv[2];
@ -596,6 +500,7 @@ struct ustorm_fcoe_task_ag_ctx {
__le32 reg5;
};
/* FCoE task context */
struct fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
@ -611,6 +516,129 @@ struct fcoe_task_context {
struct rdif_task_context rdif_context;
};
/* FCoE additional WQE (Sq/XferQ) information */
union fcoe_additional_info_union {
__le32 previous_tid;
__le32 parent_tid;
__le32 burst_length;
__le32 seq_rec_updated_offset;
};
/* FCoE Ramrod Command IDs */
enum fcoe_completion_status {
FCOE_COMPLETION_STATUS_SUCCESS,
FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
MAX_FCOE_COMPLETION_STATUS
};
/* FC address (SID/DID) network presentation */
struct fc_addr_nw {
u8 addr_lo;
u8 addr_mid;
u8 addr_hi;
};
/* FCoE connection offload */
struct fcoe_conn_offload_ramrod_data {
struct regpair sq_pbl_addr;
struct regpair sq_curr_page_addr;
struct regpair sq_next_page_addr;
struct regpair xferq_pbl_addr;
struct regpair xferq_curr_page_addr;
struct regpair xferq_next_page_addr;
struct regpair respq_pbl_addr;
struct regpair respq_curr_page_addr;
struct regpair respq_next_page_addr;
__le16 dst_mac_addr_lo;
__le16 dst_mac_addr_mid;
__le16 dst_mac_addr_hi;
__le16 src_mac_addr_lo;
__le16 src_mac_addr_mid;
__le16 src_mac_addr_hi;
__le16 tx_max_fc_pay_len;
__le16 e_d_tov_timer_val;
__le16 rx_max_fc_pay_len;
__le16 vlan_tag;
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
__le16 physical_q0;
__le16 rec_rr_tov_timer_val;
struct fc_addr_nw s_id;
u8 max_conc_seqs_c3;
struct fc_addr_nw d_id;
u8 flags;
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
__le16 conn_id;
u8 def_q_idx;
u8 reserved[5];
};
/* FCoE terminate connection request */
struct fcoe_conn_terminate_ramrod_data {
struct regpair terminate_params_addr;
};
/* Data sgl */
struct fcoe_fast_sgl_ctx {
struct regpair sgl_start_addr;
__le32 sgl_byte_offset;
__le16 task_reuse_cnt;
__le16 init_offset_in_first_sge;
};
/* FCoE firmware function init */
struct fcoe_init_func_ramrod_data {
struct scsi_init_func_params func_params;
struct scsi_init_func_queues q_params;
__le16 mtu;
__le16 sq_num_pages_in_pbl;
__le32 reserved;
};
/* FCoE: Mode of the connection: Target or Initiator or both */
enum fcoe_mode_type {
FCOE_INITIATOR_MODE = 0x0,
FCOE_TARGET_MODE = 0x1,
FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
MAX_FCOE_MODE_TYPE
};
/* Per PF FCoE receive path statistics - tStorm RAM structure */
struct fcoe_rx_stat {
struct regpair fcoe_rx_byte_cnt;
struct regpair fcoe_rx_data_pkt_cnt;
struct regpair fcoe_rx_xfer_pkt_cnt;
struct regpair fcoe_rx_other_pkt_cnt;
__le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
__le32 fcoe_silent_drop_pkt_rq_full_cnt;
__le32 fcoe_silent_drop_pkt_crc_error_cnt;
__le32 fcoe_silent_drop_pkt_task_invalid_cnt;
__le32 fcoe_silent_drop_total_pkt_cnt;
__le32 rsrv;
};
/* FCoe statistics request */
struct fcoe_stat_ramrod_data {
struct regpair stat_params_addr;
};
/* Per PF FCoE transmit path statistics - pStorm RAM structure */
struct fcoe_tx_stat {
struct regpair fcoe_tx_byte_cnt;
struct regpair fcoe_tx_data_pkt_cnt;
@ -618,6 +646,7 @@ struct fcoe_tx_stat {
struct regpair fcoe_tx_other_pkt_cnt;
};
/* FCoE SQ/XferQ element */
struct fcoe_wqe {
__le16 task_id;
__le16 flags;
@ -638,6 +667,7 @@ struct fcoe_wqe {
union fcoe_additional_info_union additional_info_union;
};
/* FCoE XFRQ element */
struct xfrqe_prot_flags {
u8 flags;
#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
@ -650,6 +680,7 @@ struct xfrqe_prot_flags {
#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
};
/* FCoE doorbell data */
struct fcoe_db_data {
u8 params;
#define FCOE_DB_DATA_DEST_MASK 0x3
@ -665,4 +696,5 @@ struct fcoe_db_data {
u8 agg_flags;
__le16 sq_prod;
};
#endif /* __FCOE_COMMON__ */

836
include/linux/qed/iscsi_common.h
View File

File diff suppressed because it is too large Load Diff

3
include/linux/qed/iwarp_common.h
View File

@ -29,9 +29,12 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __IWARP_COMMON__
#define __IWARP_COMMON__
#include <linux/qed/rdma_common.h>
/************************/
/* IWARP FW CONSTANTS */
/************************/

1
include/linux/qed/rdma_common.h
View File

@ -32,6 +32,7 @@
#ifndef __RDMA_COMMON__
#define __RDMA_COMMON__
/************************/
/* RDMA FW CONSTANTS */
/************************/

5
include/linux/qed/roce_common.h
View File

@ -33,6 +33,10 @@
#ifndef __ROCE_COMMON__
#define __ROCE_COMMON__
/************************/
/* ROCE FW CONSTANTS */
/************************/
#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
@ -40,6 +44,7 @@
#define ROCE_DCQCN_NP_MAX_QPS (64)
#define ROCE_DCQCN_RP_MAX_QPS (64)
/* Affiliated asynchronous events / errors enumeration */
enum roce_async_events_type {
ROCE_ASYNC_EVENT_NONE = 0,
ROCE_ASYNC_EVENT_COMM_EST = 1,

17
include/linux/qed/storage_common.h
View File

@ -33,6 +33,10 @@
#ifndef __STORAGE_COMMON__
#define __STORAGE_COMMON__
/*********************/
/* SCSI CONSTANTS */
/*********************/
#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
#define BDQ_NUM_RESOURCES (4)
@ -42,34 +46,40 @@
#define SCSI_NUM_SGES_SLOW_SGL_THR 8
#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15)
#define BDQ_MAX_EXTERNAL_RING_SIZE BIT(15)
/* SCSI buffer descriptor */
struct scsi_bd {
struct regpair address;
struct regpair opaque;
};
/* Scsi Drv BDQ struct */
struct scsi_bdq_ram_drv_data {
__le16 external_producer;
__le16 reserved0[3];
};
/* SCSI SGE entry */
struct scsi_sge {
struct regpair sge_addr;
__le32 sge_len;
__le32 reserved;
};
/* Cached SGEs section */
struct scsi_cached_sges {
struct scsi_sge sge[4];
};
/* Scsi Drv CMDQ struct */
struct scsi_drv_cmdq {
__le16 cmdq_cons;
__le16 reserved0;
__le32 reserved1;
};
/* Common SCSI init params passed by driver to FW in function init ramrod */
struct scsi_init_func_params {
__le16 num_tasks;
u8 log_page_size;
@ -77,6 +87,7 @@ struct scsi_init_func_params {
u8 reserved2[12];
};
/* SCSI RQ/CQ/CMDQ firmware function init parameters */
struct scsi_init_func_queues {
struct regpair glbl_q_params_addr;
__le16 rq_buffer_size;
@ -107,16 +118,19 @@ struct scsi_init_func_queues {
__le32 reserved1;
};
/* Scsi Drv BDQ Data struct (2 BDQ IDs: 0 - RQ, 1 - Immediate Data) */
struct scsi_ram_per_bdq_resource_drv_data {
struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
};
/* SCSI SGL types */
enum scsi_sgl_mode {
SCSI_TX_SLOW_SGL,
SCSI_FAST_SGL,
MAX_SCSI_SGL_MODE
};
/* SCSI SGL parameters */
struct scsi_sgl_params {
struct regpair sgl_addr;
__le32 sgl_total_length;
@ -126,6 +140,7 @@ struct scsi_sgl_params {
u8 reserved;
};
/* SCSI terminate connection params */
struct scsi_terminate_extra_params {
__le16 unsolicited_cq_count;
__le16 cmdq_count;

15
include/linux/qed/tcp_common.h
View File

@ -33,8 +33,13 @@
#ifndef __TCP_COMMON__
#define __TCP_COMMON__
/********************/
/* TCP FW CONSTANTS */
/********************/
#define TCP_INVALID_TIMEOUT_VAL -1
/* OOO opaque data received from LL2 */
struct ooo_opaque {
__le32 cid;
u8 drop_isle;
@ -43,25 +48,29 @@ struct ooo_opaque {
u8 ooo_isle;
};
/* tcp connect mode enum */
enum tcp_connect_mode {
TCP_CONNECT_ACTIVE,
TCP_CONNECT_PASSIVE,
MAX_TCP_CONNECT_MODE
};
/* tcp function init parameters */
struct tcp_init_params {
__le32 two_msl_timer;
__le16 tx_sws_timer;
u8 maxfinrt;
u8 max_fin_rt;
u8 reserved[9];
};
/* tcp IPv4/IPv6 enum */
enum tcp_ip_version {
TCP_IPV4,
TCP_IPV6,
MAX_TCP_IP_VERSION
};
/* tcp offload parameters */
struct tcp_offload_params {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
@ -132,6 +141,7 @@ struct tcp_offload_params {
__le32 reserved3[2];
};
/* tcp offload parameters */
struct tcp_offload_params_opt2 {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
@ -166,6 +176,7 @@ struct tcp_offload_params_opt2 {
__le32 reserved1[22];
};
/* tcp IPv4/IPv6 enum */
enum tcp_seg_placement_event {
TCP_EVENT_ADD_PEN,
TCP_EVENT_ADD_NEW_ISLE,
@ -177,6 +188,7 @@ enum tcp_seg_placement_event {
MAX_TCP_SEG_PLACEMENT_EVENT
};
/* tcp init parameters */
struct tcp_update_params {
__le16 flags;
#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
@ -226,6 +238,7 @@ struct tcp_update_params {
u8 reserved1[7];
};
/* toe upload parameters */
struct tcp_upload_params {
__le32 rcv_next;
__le32 snd_una;