MIPS: tlbex: Better debug output.
Pgtable bits are assigned dynamically depending on processor feature and statically based on kernel configuration. To make sense out of the disassembled TLB exception handlers a list of the actual assignments used for a particular configuration and hardware setup can be very useful. Output the actual TLB exception handlers in a format that simplifies their post processsing from dmesg output. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
088b530a07
commit
a2c763e074
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@ -34,38 +34,72 @@
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*/
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define _PAGE_PRESENT (1<<6) /* implemented in software */
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#define _PAGE_READ (1<<7) /* implemented in software */
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#define _PAGE_WRITE (1<<8) /* implemented in software */
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#define _PAGE_ACCESSED (1<<9) /* implemented in software */
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#define _PAGE_MODIFIED (1<<10) /* implemented in software */
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#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
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/*
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* The following bits are directly used by the TLB hardware
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*/
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#define _PAGE_R4KBUG (1 << 0) /* workaround for r4k bug */
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#define _PAGE_GLOBAL (1 << 0)
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#define _PAGE_VALID_SHIFT 1
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#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
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#define _PAGE_SILENT_READ (1 << 1) /* synonym */
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#define _PAGE_DIRTY_SHIFT 2
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#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1 << 2)
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#define _CACHE_SHIFT 3
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#define _CACHE_MASK (7 << 3)
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#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
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#define _PAGE_GLOBAL (1<<0)
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#define _PAGE_VALID (1<<1)
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#define _PAGE_SILENT_READ (1<<1) /* synonym */
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#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<2)
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#define _CACHE_SHIFT 3
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#define _CACHE_MASK (7<<3)
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/*
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* The following bits are implemented in software
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*
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* _PAGE_FILE semantics: set:pagecache unset:swap
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*/
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#define _PAGE_PRESENT_SHIFT 6
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#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
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#define _PAGE_READ_SHIFT 7
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#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
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#define _PAGE_WRITE_SHIFT 8
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#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
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#define _PAGE_ACCESSED_SHIFT 9
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#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
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#define _PAGE_MODIFIED_SHIFT 10
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#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
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#define _PAGE_FILE (1 << 10)
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#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _PAGE_PRESENT (1<<0) /* implemented in software */
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#define _PAGE_READ (1<<1) /* implemented in software */
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#define _PAGE_WRITE (1<<2) /* implemented in software */
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#define _PAGE_ACCESSED (1<<3) /* implemented in software */
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#define _PAGE_MODIFIED (1<<4) /* implemented in software */
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#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */
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/*
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* The following are implemented by software
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*
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* _PAGE_FILE semantics: set:pagecache unset:swap
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*/
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#define _PAGE_PRESENT_SHIFT 0
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#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
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#define _PAGE_READ_SHIFT 1
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#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
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#define _PAGE_WRITE_SHIFT 2
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#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
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#define _PAGE_ACCESSED_SHIFT 3
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#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
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#define _PAGE_MODIFIED_SHIFT 4
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#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
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#define _PAGE_FILE_SHIFT 4
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#define _PAGE_FILE (1 << _PAGE_FILE_SHIFT)
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#define _PAGE_GLOBAL (1<<8)
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#define _PAGE_VALID (1<<9)
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#define _PAGE_SILENT_READ (1<<9) /* synonym */
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#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<10)
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#define _CACHE_UNCACHED (1<<11)
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#define _CACHE_MASK (1<<11)
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/*
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* And these are the hardware TLB bits
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*/
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#define _PAGE_GLOBAL_SHIFT 8
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#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
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#define _PAGE_VALID_SHIFT 9
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#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
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#define _PAGE_SILENT_READ (1 << _PAGE_VALID_SHIFT) /* synonym */
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#define _PAGE_DIRTY_SHIFT 10
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#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
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#define _PAGE_SILENT_WRITE (1 << _PAGE_DIRTY_SHIFT)
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#define _CACHE_UNCACHED_SHIFT 11
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#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
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#define _CACHE_MASK (1 << _CACHE_UNCACHED_SHIFT)
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#else /* 'Normal' r4K case */
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/*
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@ -76,22 +110,22 @@
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* which is more than we need right now.
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*/
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/* implemented in software */
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/*
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* The following bits are implemented in software
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*
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* _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
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* _PAGE_FILE semantics: set:pagecache unset:swap
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*/
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#define _PAGE_PRESENT_SHIFT (0)
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#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
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/* implemented in software, should be unused if cpu_has_rixi. */
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#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
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#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
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/* implemented in software */
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#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
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#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
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/* implemented in software */
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#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
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#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
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/* implemented in software */
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#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
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#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
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/* set:pagecache unset:swap */
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#define _PAGE_FILE (_PAGE_MODIFIED)
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#ifdef CONFIG_HUGETLB_PAGE
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@ -206,19 +206,58 @@ static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
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}
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/*
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* For debug purposes.
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* pgtable bits are assigned dynamically depending on processor feature
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* and statically based on kernel configuration. This spits out the actual
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* values the kernel is using. Required to make sense from disassembled
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* TLB exception handlers.
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*/
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static inline void dump_handler(const u32 *handler, int count)
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static void output_pgtable_bits_defines(void)
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{
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#define pr_define(fmt, ...) \
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pr_debug("#define " fmt, ##__VA_ARGS__)
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pr_debug("#include <asm/asm.h>\n");
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pr_debug("#include <asm/regdef.h>\n");
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pr_debug("\n");
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pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
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pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
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pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
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pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
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pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
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#ifdef _PAGE_HUGE_SHIFT
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pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
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#endif
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if (cpu_has_rixi) {
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#ifdef _PAGE_NO_EXEC_SHIFT
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pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
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#endif
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#ifdef _PAGE_NO_READ_SHIFT
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pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
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#endif
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}
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pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
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pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
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pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
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pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
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pr_debug("\n");
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}
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static inline void dump_handler(const char *symbol, const u32 *handler, int count)
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{
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int i;
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pr_debug("LEAF(%s)\n", symbol);
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pr_debug("\t.set push\n");
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pr_debug("\t.set noreorder\n");
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for (i = 0; i < count; i++)
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pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
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pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
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pr_debug("\t.set pop\n");
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pr_debug("\t.set\tpop\n");
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pr_debug("\tEND(%s)\n", symbol);
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}
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/* The only general purpose registers allowed in TLB handlers. */
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@ -401,7 +440,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
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memcpy((void *)ebase, tlb_handler, 0x80);
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dump_handler((u32 *)ebase, 32);
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dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
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}
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
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@ -1434,7 +1473,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
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memcpy((void *)ebase, final_handler, 0x100);
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dump_handler((u32 *)ebase, 64);
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dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
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}
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/*
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@ -1491,7 +1530,8 @@ static void __cpuinit build_r4000_setup_pgd(void)
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pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
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(unsigned int)(p - tlbmiss_handler_setup_pgd));
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dump_handler(tlbmiss_handler_setup_pgd,
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dump_handler("tlbmiss_handler",
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tlbmiss_handler_setup_pgd,
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ARRAY_SIZE(tlbmiss_handler_setup_pgd));
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}
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#endif
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@ -1761,7 +1801,7 @@ static void __cpuinit build_r3000_tlb_load_handler(void)
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pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
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(unsigned int)(p - handle_tlbl));
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dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
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dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
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}
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static void __cpuinit build_r3000_tlb_store_handler(void)
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@ -1791,7 +1831,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void)
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pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
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(unsigned int)(p - handle_tlbs));
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dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
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dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
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}
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static void __cpuinit build_r3000_tlb_modify_handler(void)
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@ -1821,7 +1861,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
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pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
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(unsigned int)(p - handle_tlbm));
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dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
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dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
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}
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
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@ -2028,7 +2068,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
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pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
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(unsigned int)(p - handle_tlbl));
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dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
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dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
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}
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static void __cpuinit build_r4000_tlb_store_handler(void)
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@ -2075,7 +2115,7 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
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pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
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(unsigned int)(p - handle_tlbs));
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dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
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dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
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}
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static void __cpuinit build_r4000_tlb_modify_handler(void)
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@ -2123,7 +2163,7 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
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pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
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(unsigned int)(p - handle_tlbm));
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dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
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dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
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}
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void __cpuinit build_tlb_refill_handler(void)
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@ -2135,6 +2175,8 @@ void __cpuinit build_tlb_refill_handler(void)
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*/
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static int run_once = 0;
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output_pgtable_bits_defines();
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#ifdef CONFIG_64BIT
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check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
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#endif
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