crypto: atmel-sha - update request queue management to make it more generic
This patch is a transitional patch. It splits the atmel_sha_handle_queue() function. Now atmel_sha_handle_queue() only manages the request queue and calls a new .start() hook from the atmel_sha_ctx structure. This hook allows to implement different kind of requests still handled by a single queue. Also when the req parameter of atmel_sha_handle_queue() refers to the very same request as the one returned by crypto_dequeue_request(), the queue management now gives a chance to this crypto request to be handled synchronously, hence reducing latencies. The .start() hook returns 0 if the crypto request was handled synchronously and -EINPROGRESS if the crypto request still need to be handled asynchronously. Besides, the new .is_async member of the atmel_sha_dev structure helps tagging this asynchronous state. Indeed, the req->base.complete() callback should not be called if the crypto request is handled synchronously. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -105,8 +105,11 @@ struct atmel_sha_reqctx {
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u8 buffer[SHA_BUFFER_LEN + SHA512_BLOCK_SIZE] __aligned(sizeof(u32));
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};
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typedef int (*atmel_sha_fn_t)(struct atmel_sha_dev *);
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struct atmel_sha_ctx {
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struct atmel_sha_dev *dd;
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atmel_sha_fn_t start;
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unsigned long flags;
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};
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@ -134,6 +137,7 @@ struct atmel_sha_dev {
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unsigned long flags;
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struct crypto_queue queue;
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struct ahash_request *req;
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bool is_async;
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struct atmel_sha_dma dma_lch_in;
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@ -163,6 +167,24 @@ static inline void atmel_sha_write(struct atmel_sha_dev *dd,
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writel_relaxed(value, dd->io_base + offset);
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}
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static inline int atmel_sha_complete(struct atmel_sha_dev *dd, int err)
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{
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struct ahash_request *req = dd->req;
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dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
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SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY);
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clk_disable(dd->iclk);
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if (dd->is_async && req->base.complete)
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req->base.complete(&req->base, err);
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/* handle new request */
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tasklet_schedule(&dd->queue_task);
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return err;
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}
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static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
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{
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size_t count;
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@ -474,6 +496,8 @@ static void atmel_sha_dma_callback(void *data)
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{
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struct atmel_sha_dev *dd = data;
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dd->is_async = true;
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/* dma_lch_in - completed - wait DATRDY */
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atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
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}
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@ -509,7 +533,7 @@ static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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}
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if (!in_desc)
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return -EINVAL;
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atmel_sha_complete(dd, -EINVAL);
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in_desc->callback = atmel_sha_dma_callback;
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in_desc->callback_param = dd;
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@ -566,7 +590,7 @@ static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
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if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
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dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen +
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ctx->block_size);
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return -EINVAL;
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atmel_sha_complete(dd, -EINVAL);
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}
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ctx->flags &= ~SHA_FLAGS_SG;
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@ -657,7 +681,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
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if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
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dev_err(dd->dev, "dma %u bytes error\n",
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ctx->buflen + ctx->block_size);
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return -EINVAL;
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atmel_sha_complete(dd, -EINVAL);
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}
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if (length == 0) {
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@ -671,7 +695,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
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if (!dma_map_sg(dd->dev, ctx->sg, 1,
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DMA_TO_DEVICE)) {
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dev_err(dd->dev, "dma_map_sg error\n");
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return -EINVAL;
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atmel_sha_complete(dd, -EINVAL);
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}
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ctx->flags |= SHA_FLAGS_SG;
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@ -685,7 +709,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
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if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
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dev_err(dd->dev, "dma_map_sg error\n");
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return -EINVAL;
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atmel_sha_complete(dd, -EINVAL);
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}
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ctx->flags |= SHA_FLAGS_SG;
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@ -843,16 +867,7 @@ static void atmel_sha_finish_req(struct ahash_request *req, int err)
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}
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/* atomic operation is not needed here */
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dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
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SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY);
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clk_disable(dd->iclk);
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if (req->base.complete)
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req->base.complete(&req->base, err);
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/* handle new request */
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tasklet_schedule(&dd->queue_task);
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(void)atmel_sha_complete(dd, err);
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}
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static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
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@ -893,8 +908,9 @@ static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
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struct ahash_request *req)
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{
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struct crypto_async_request *async_req, *backlog;
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struct atmel_sha_reqctx *ctx;
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struct atmel_sha_ctx *ctx;
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unsigned long flags;
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bool start_async;
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int err = 0, ret = 0;
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spin_lock_irqsave(&dd->lock, flags);
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@ -919,9 +935,22 @@ static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
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if (backlog)
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backlog->complete(backlog, -EINPROGRESS);
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req = ahash_request_cast(async_req);
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dd->req = req;
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ctx = ahash_request_ctx(req);
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ctx = crypto_tfm_ctx(async_req->tfm);
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dd->req = ahash_request_cast(async_req);
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start_async = (dd->req != req);
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dd->is_async = start_async;
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/* WARNING: ctx->start() MAY change dd->is_async. */
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err = ctx->start(dd);
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return (start_async) ? ret : err;
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}
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static int atmel_sha_start(struct atmel_sha_dev *dd)
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{
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struct ahash_request *req = dd->req;
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struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
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int err;
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dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
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ctx->op, req->nbytes);
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@ -947,7 +976,7 @@ err1:
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dev_dbg(dd->dev, "exit, err: %d\n", err);
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return ret;
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return err;
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}
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static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op)
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@ -1043,8 +1072,11 @@ static int atmel_sha_import(struct ahash_request *req, const void *in)
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static int atmel_sha_cra_init(struct crypto_tfm *tfm)
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{
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struct atmel_sha_ctx *ctx = crypto_tfm_ctx(tfm);
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crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
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sizeof(struct atmel_sha_reqctx));
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ctx->start = atmel_sha_start;
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return 0;
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}
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@ -1188,6 +1220,8 @@ static void atmel_sha_done_task(unsigned long data)
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struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
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int err = 0;
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dd->is_async = true;
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if (SHA_FLAGS_CPU & dd->flags) {
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if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
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dd->flags &= ~SHA_FLAGS_OUTPUT_READY;
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