locking/atomic, arch/powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()
Implement FETCH-OP atomic primitives, these are very similar to the existing OP-RETURN primitives we already have, except they return the value of the atomic variable _before_ modification. This is especially useful for irreversible operations -- such as bitops (because it becomes impossible to reconstruct the state prior to modification). Tested-by: Boqun Feng <boqun.feng@gmail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -78,21 +78,53 @@ static inline int atomic_##op##_return_relaxed(int a, atomic_t *v) \
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return t; \
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}
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#define ATOMIC_FETCH_OP_RELAXED(op, asm_op) \
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static inline int atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
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{ \
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int res, t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%4 # atomic_fetch_" #op "_relaxed\n" \
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#asm_op " %1,%3,%0\n" \
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PPC405_ERR77(0, %4) \
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" stwcx. %1,0,%4\n" \
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" bne- 1b\n" \
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: "=&r" (res), "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return res; \
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}
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_OP_RETURN_RELAXED(op, asm_op)
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ATOMIC_OP_RETURN_RELAXED(op, asm_op) \
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ATOMIC_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, subf)
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ATOMIC_OP(and, and)
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ATOMIC_OP(or, or)
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ATOMIC_OP(xor, xor)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC_OPS(and, and)
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ATOMIC_OPS(or, or)
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ATOMIC_OPS(xor, xor)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP_RELAXED
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#undef ATOMIC_OP_RETURN_RELAXED
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#undef ATOMIC_OP
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@ -329,20 +361,53 @@ atomic64_##op##_return_relaxed(long a, atomic64_t *v) \
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return t; \
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}
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#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op) \
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static inline long \
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atomic64_fetch_##op##_relaxed(long a, atomic64_t *v) \
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{ \
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long res, t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%4 # atomic64_fetch_" #op "_relaxed\n" \
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#asm_op " %1,%3,%0\n" \
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" stdcx. %1,0,%4\n" \
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" bne- 1b\n" \
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: "=&r" (res), "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return res; \
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}
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_OP_RETURN_RELAXED(op, asm_op)
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ATOMIC64_OP_RETURN_RELAXED(op, asm_op) \
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ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC64_OPS(add, add)
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ATOMIC64_OPS(sub, subf)
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ATOMIC64_OP(and, and)
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ATOMIC64_OP(or, or)
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ATOMIC64_OP(xor, xor)
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC64_OPS(and, and)
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ATOMIC64_OPS(or, or)
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ATOMIC64_OPS(xor, xor)
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#undef ATOPIC64_OPS
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#undef ATOMIC64_FETCH_OP_RELAXED
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#undef ATOMIC64_OP_RETURN_RELAXED
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#undef ATOMIC64_OP
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