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Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze 

* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
  microblaze: Fix msr instruction detection
  microblaze: Fix pte_update function
  microblaze: Fix asm compilation warning
  microblaze: Fix IRQ flag handling for MSR=0
This commit is contained in:
Linus Torvalds 2011-02-11 16:13:53 -08:00
parent 80d02d2736 0eb6aaf529
commit a288465fa8
5 changed files with 24 additions and 26 deletions
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2
arch/microblaze/include/asm/irqflags.h
View File

@ -12,7 +12,7 @@
#include <linux/types.h>
#include <asm/registers.h>
#ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
static inline unsigned long arch_local_irq_save(void)
{

23
arch/microblaze/include/asm/pgtable.h
View File

@ -411,21 +411,20 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
static inline unsigned long pte_update(pte_t *p, unsigned long clr,
unsigned long set)
{
unsigned long old, tmp, msr;
unsigned long flags, old, tmp;
__asm__ __volatile__("\
msrclr %2, 0x2\n\
nop\n\
lw %0, %4, r0\n\
andn %1, %0, %5\n\
or %1, %1, %6\n\
sw %1, %4, r0\n\
mts rmsr, %2\n\
nop"
: "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p)
: "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p)
raw_local_irq_save(flags);
__asm__ __volatile__( "lw %0, %2, r0 \n"
"andn %1, %0, %3 \n"
"or %1, %1, %4 \n"
"sw %1, %2, r0 \n"
: "=&r" (old), "=&r" (tmp)
: "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
: "cc");
raw_local_irq_restore(flags);
return old;
}

2
arch/microblaze/kernel/cpu/pvr.c
View File

@ -54,7 +54,7 @@ int cpu_has_pvr(void)
if (!(flags & PVR_MSR_BIT))
return 0;
get_single_pvr(0x00, pvr0);
get_single_pvr(0, pvr0);
pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
if (pvr0 & PVR0_PVR_FULL_MASK)

15
arch/microblaze/kernel/head.S
View File

@ -62,15 +62,14 @@ real_start:
andi r1, r1, ~2
mts rmsr, r1
/*
* Here is checking mechanism which check if Microblaze has msr instructions
* We load msr and compare it with previous r1 value - if is the same,
* msr instructions works if not - cpu don't have them.
* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
* if the msrclr instruction is not enabled. We use this to detect
* if the opcode is available, by issuing msrclr and then testing the result.
* r8 == 0 - msr instructions are implemented
* r8 != 0 - msr instructions are not implemented
*/
/* r8=0 - I have msr instr, 1 - I don't have them */
rsubi r0, r0, 1 /* set the carry bit */
msrclr r0, 0x4 /* try to clear it */
/* read the carry bit, r8 will be '0' if msrclr exists */
addik r8, r0, 0
msrclr r8, 0 /* clear nothing - just read msr for test */
cmpu r8, r8, r1 /* r1 must contain msr reg content */
/* r7 may point to an FDT, or there may be one linked in.
if it's in r7, we've got to save it away ASAP.

4
arch/microblaze/kernel/setup.c
View File

@ -161,11 +161,11 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
if (msr)
eprintk("!!!Your kernel has setup MSR instruction but "
"CPU don't have it %d\n", msr);
"CPU don't have it %x\n", msr);
#else
if (!msr)
eprintk("!!!Your kernel not setup MSR instruction but "
"CPU have it %d\n", msr);
"CPU have it %x\n", msr);
#endif
for (src = __ivt_start; src < __ivt_end; src++, dst++)