locking/pvqspinlock: Implement simple paravirt support for the qspinlock
Provide a separate (second) version of the spin_lock_slowpath for paravirt along with a special unlock path. The second slowpath is generated by adding a few pv hooks to the normal slowpath, but where those will compile away for the native case, they expand into special wait/wake code for the pv version. The actual MCS queue can use extra storage in the mcs_nodes[] array to keep track of state and therefore uses directed wakeups. The head contender has no such storage directly visible to the unlocker. So the unlocker searches a hash table with open addressing using a simple binary Galois linear feedback shift register. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Waiman Long <Waiman.Long@hp.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Daniel J Blueman <daniel@numascale.com> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Douglas Hatch <doug.hatch@hp.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Paolo Bonzini <paolo.bonzini@gmail.com> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com> Cc: Rik van Riel <riel@redhat.com> Cc: Scott J Norton <scott.norton@hp.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1429901803-29771-9-git-send-email-Waiman.Long@hp.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Waiman Long
Ingo Molnar
parent
2aa79af642
commit
a23db284fe
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@ -18,6 +18,9 @@
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* Authors: Waiman Long <waiman.long@hp.com>
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* Peter Zijlstra <peterz@infradead.org>
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*/
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#ifndef _GEN_PV_LOCK_SLOWPATH
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#include <linux/smp.h>
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#include <linux/bug.h>
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#include <linux/cpumask.h>
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@ -65,13 +68,21 @@
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#include "mcs_spinlock.h"
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define MAX_NODES 8
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#else
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#define MAX_NODES 4
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#endif
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/*
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* Per-CPU queue node structures; we can never have more than 4 nested
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* contexts: task, softirq, hardirq, nmi.
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*
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* Exactly fits one 64-byte cacheline on a 64-bit architecture.
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*
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* PV doubles the storage and uses the second cacheline for PV state.
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*/
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static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[4]);
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static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[MAX_NODES]);
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/*
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* We must be able to distinguish between no-tail and the tail at 0:0,
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@ -220,6 +231,32 @@ static __always_inline void set_locked(struct qspinlock *lock)
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WRITE_ONCE(l->locked, _Q_LOCKED_VAL);
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}
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/*
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* Generate the native code for queued_spin_unlock_slowpath(); provide NOPs for
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* all the PV callbacks.
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*/
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static __always_inline void __pv_init_node(struct mcs_spinlock *node) { }
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static __always_inline void __pv_wait_node(struct mcs_spinlock *node) { }
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static __always_inline void __pv_kick_node(struct mcs_spinlock *node) { }
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static __always_inline void __pv_wait_head(struct qspinlock *lock,
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struct mcs_spinlock *node) { }
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#define pv_enabled() false
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#define pv_init_node __pv_init_node
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#define pv_wait_node __pv_wait_node
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#define pv_kick_node __pv_kick_node
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#define pv_wait_head __pv_wait_head
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define queued_spin_lock_slowpath native_queued_spin_lock_slowpath
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#endif
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#endif /* _GEN_PV_LOCK_SLOWPATH */
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/**
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* queued_spin_lock_slowpath - acquire the queued spinlock
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* @lock: Pointer to queued spinlock structure
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@ -249,6 +286,9 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS));
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if (pv_enabled())
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goto queue;
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if (virt_queued_spin_lock(lock))
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return;
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@ -325,6 +365,7 @@ queue:
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node += idx;
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node->locked = 0;
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node->next = NULL;
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pv_init_node(node);
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/*
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* We touched a (possibly) cold cacheline in the per-cpu queue node;
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@ -350,6 +391,7 @@ queue:
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prev = decode_tail(old);
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WRITE_ONCE(prev->next, node);
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pv_wait_node(node);
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arch_mcs_spin_lock_contended(&node->locked);
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}
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@ -365,6 +407,7 @@ queue:
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* does not imply a full barrier.
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*
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*/
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pv_wait_head(lock, node);
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while ((val = smp_load_acquire(&lock->val.counter)) & _Q_LOCKED_PENDING_MASK)
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cpu_relax();
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@ -397,6 +440,7 @@ queue:
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cpu_relax();
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arch_mcs_spin_unlock_contended(&next->locked);
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pv_kick_node(next);
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release:
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/*
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@ -405,3 +449,25 @@ release:
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this_cpu_dec(mcs_nodes[0].count);
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}
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EXPORT_SYMBOL(queued_spin_lock_slowpath);
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/*
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* Generate the paravirt code for queued_spin_unlock_slowpath().
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*/
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#if !defined(_GEN_PV_LOCK_SLOWPATH) && defined(CONFIG_PARAVIRT_SPINLOCKS)
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#define _GEN_PV_LOCK_SLOWPATH
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#undef pv_enabled
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#define pv_enabled() true
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#undef pv_init_node
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#undef pv_wait_node
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#undef pv_kick_node
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#undef pv_wait_head
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#undef queued_spin_lock_slowpath
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#define queued_spin_lock_slowpath __pv_queued_spin_lock_slowpath
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#include "qspinlock_paravirt.h"
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#include "qspinlock.c"
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#endif
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@ -0,0 +1,325 @@
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#ifndef _GEN_PV_LOCK_SLOWPATH
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#error "do not include this file"
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#endif
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#include <linux/hash.h>
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#include <linux/bootmem.h>
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/*
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* Implement paravirt qspinlocks; the general idea is to halt the vcpus instead
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* of spinning them.
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*
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* This relies on the architecture to provide two paravirt hypercalls:
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*
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* pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
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* pv_kick(cpu) -- wakes a suspended vcpu
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*
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* Using these we implement __pv_queued_spin_lock_slowpath() and
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* __pv_queued_spin_unlock() to replace native_queued_spin_lock_slowpath() and
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* native_queued_spin_unlock().
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*/
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#define _Q_SLOW_VAL (3U << _Q_LOCKED_OFFSET)
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enum vcpu_state {
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vcpu_running = 0,
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vcpu_halted,
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};
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struct pv_node {
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struct mcs_spinlock mcs;
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struct mcs_spinlock __res[3];
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int cpu;
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u8 state;
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};
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/*
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* Lock and MCS node addresses hash table for fast lookup
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*
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* Hashing is done on a per-cacheline basis to minimize the need to access
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* more than one cacheline.
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*
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* Dynamically allocate a hash table big enough to hold at least 4X the
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* number of possible cpus in the system. Allocation is done on page
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* granularity. So the minimum number of hash buckets should be at least
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* 256 (64-bit) or 512 (32-bit) to fully utilize a 4k page.
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*
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* Since we should not be holding locks from NMI context (very rare indeed) the
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* max load factor is 0.75, which is around the point where open addressing
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* breaks down.
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*
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*/
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struct pv_hash_entry {
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struct qspinlock *lock;
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struct pv_node *node;
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};
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#define PV_HE_PER_LINE (SMP_CACHE_BYTES / sizeof(struct pv_hash_entry))
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#define PV_HE_MIN (PAGE_SIZE / sizeof(struct pv_hash_entry))
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static struct pv_hash_entry *pv_lock_hash;
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static unsigned int pv_lock_hash_bits __read_mostly;
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/*
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* Allocate memory for the PV qspinlock hash buckets
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*
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* This function should be called from the paravirt spinlock initialization
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* routine.
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*/
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void __init __pv_init_lock_hash(void)
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{
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int pv_hash_size = ALIGN(4 * num_possible_cpus(), PV_HE_PER_LINE);
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if (pv_hash_size < PV_HE_MIN)
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pv_hash_size = PV_HE_MIN;
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/*
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* Allocate space from bootmem which should be page-size aligned
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* and hence cacheline aligned.
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*/
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pv_lock_hash = alloc_large_system_hash("PV qspinlock",
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sizeof(struct pv_hash_entry),
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pv_hash_size, 0, HASH_EARLY,
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&pv_lock_hash_bits, NULL,
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pv_hash_size, pv_hash_size);
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}
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#define for_each_hash_entry(he, offset, hash) \
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for (hash &= ~(PV_HE_PER_LINE - 1), he = &pv_lock_hash[hash], offset = 0; \
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offset < (1 << pv_lock_hash_bits); \
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offset++, he = &pv_lock_hash[(hash + offset) & ((1 << pv_lock_hash_bits) - 1)])
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static struct qspinlock **pv_hash(struct qspinlock *lock, struct pv_node *node)
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{
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unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits);
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struct pv_hash_entry *he;
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for_each_hash_entry(he, offset, hash) {
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if (!cmpxchg(&he->lock, NULL, lock)) {
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WRITE_ONCE(he->node, node);
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return &he->lock;
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}
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}
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/*
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* Hard assume there is a free entry for us.
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*
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* This is guaranteed by ensuring every blocked lock only ever consumes
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* a single entry, and since we only have 4 nesting levels per CPU
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* and allocated 4*nr_possible_cpus(), this must be so.
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*
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* The single entry is guaranteed by having the lock owner unhash
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* before it releases.
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*/
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BUG();
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}
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static struct pv_node *pv_unhash(struct qspinlock *lock)
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{
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unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits);
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struct pv_hash_entry *he;
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struct pv_node *node;
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for_each_hash_entry(he, offset, hash) {
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if (READ_ONCE(he->lock) == lock) {
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node = READ_ONCE(he->node);
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WRITE_ONCE(he->lock, NULL);
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return node;
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}
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}
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/*
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* Hard assume we'll find an entry.
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*
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* This guarantees a limited lookup time and is itself guaranteed by
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* having the lock owner do the unhash -- IFF the unlock sees the
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* SLOW flag, there MUST be a hash entry.
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*/
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BUG();
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}
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/*
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* Initialize the PV part of the mcs_spinlock node.
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*/
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static void pv_init_node(struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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BUILD_BUG_ON(sizeof(struct pv_node) > 5*sizeof(struct mcs_spinlock));
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pn->cpu = smp_processor_id();
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pn->state = vcpu_running;
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}
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/*
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* Wait for node->locked to become true, halt the vcpu after a short spin.
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* pv_kick_node() is used to wake the vcpu again.
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*/
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static void pv_wait_node(struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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int loop;
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for (;;) {
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for (loop = SPIN_THRESHOLD; loop; loop--) {
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if (READ_ONCE(node->locked))
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return;
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cpu_relax();
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}
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/*
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* Order pn->state vs pn->locked thusly:
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*
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* [S] pn->state = vcpu_halted [S] next->locked = 1
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* MB MB
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* [L] pn->locked [RmW] pn->state = vcpu_running
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*
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* Matches the xchg() from pv_kick_node().
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*/
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(void)xchg(&pn->state, vcpu_halted);
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if (!READ_ONCE(node->locked))
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pv_wait(&pn->state, vcpu_halted);
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/*
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* Reset the vCPU state to avoid unncessary CPU kicking
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*/
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WRITE_ONCE(pn->state, vcpu_running);
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/*
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* If the locked flag is still not set after wakeup, it is a
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* spurious wakeup and the vCPU should wait again. However,
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* there is a pretty high overhead for CPU halting and kicking.
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* So it is better to spin for a while in the hope that the
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* MCS lock will be released soon.
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*/
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}
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/*
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* By now our node->locked should be 1 and our caller will not actually
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* spin-wait for it. We do however rely on our caller to do a
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* load-acquire for us.
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*/
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}
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/*
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* Called after setting next->locked = 1, used to wake those stuck in
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* pv_wait_node().
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*/
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static void pv_kick_node(struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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/*
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* Note that because node->locked is already set, this actual
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* mcs_spinlock entry could be re-used already.
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*
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* This should be fine however, kicking people for no reason is
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* harmless.
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*
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* See the comment in pv_wait_node().
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*/
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if (xchg(&pn->state, vcpu_running) == vcpu_halted)
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pv_kick(pn->cpu);
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}
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/*
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* Wait for l->locked to become clear; halt the vcpu after a short spin.
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* __pv_queued_spin_unlock() will wake us.
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*/
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static void pv_wait_head(struct qspinlock *lock, struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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struct __qspinlock *l = (void *)lock;
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struct qspinlock **lp = NULL;
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int loop;
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for (;;) {
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for (loop = SPIN_THRESHOLD; loop; loop--) {
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if (!READ_ONCE(l->locked))
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return;
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cpu_relax();
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}
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WRITE_ONCE(pn->state, vcpu_halted);
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if (!lp) { /* ONCE */
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lp = pv_hash(lock, pn);
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/*
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* lp must be set before setting _Q_SLOW_VAL
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*
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* [S] lp = lock [RmW] l = l->locked = 0
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* MB MB
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* [S] l->locked = _Q_SLOW_VAL [L] lp
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*
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* Matches the cmpxchg() in __pv_queued_spin_unlock().
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*/
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if (!cmpxchg(&l->locked, _Q_LOCKED_VAL, _Q_SLOW_VAL)) {
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/*
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* The lock is free and _Q_SLOW_VAL has never
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* been set. Therefore we need to unhash before
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* getting the lock.
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*/
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WRITE_ONCE(*lp, NULL);
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return;
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}
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}
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pv_wait(&l->locked, _Q_SLOW_VAL);
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/*
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* The unlocker should have freed the lock before kicking the
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* CPU. So if the lock is still not free, it is a spurious
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* wakeup and so the vCPU should wait again after spinning for
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* a while.
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*/
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}
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/*
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* Lock is unlocked now; the caller will acquire it without waiting.
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* As with pv_wait_node() we rely on the caller to do a load-acquire
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* for us.
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*/
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}
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/*
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* PV version of the unlock function to be used in stead of
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* queued_spin_unlock().
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*/
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__visible void __pv_queued_spin_unlock(struct qspinlock *lock)
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{
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struct __qspinlock *l = (void *)lock;
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struct pv_node *node;
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/*
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* We must not unlock if SLOW, because in that case we must first
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* unhash. Otherwise it would be possible to have multiple @lock
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* entries, which would be BAD.
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*/
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if (likely(cmpxchg(&l->locked, _Q_LOCKED_VAL, 0) == _Q_LOCKED_VAL))
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return;
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/*
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* Since the above failed to release, this must be the SLOW path.
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* Therefore start by looking up the blocked node and unhashing it.
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*/
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node = pv_unhash(lock);
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/*
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* Now that we have a reference to the (likely) blocked pv_node,
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* release the lock.
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*/
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smp_store_release(&l->locked, 0);
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/*
|
||||
* At this point the memory pointed at by lock can be freed/reused,
|
||||
* however we can still use the pv_node to kick the CPU.
|
||||
*/
|
||||
if (READ_ONCE(node->state) == vcpu_halted)
|
||||
pv_kick(node->cpu);
|
||||
}
|
||||
/*
|
||||
* Include the architecture specific callee-save thunk of the
|
||||
* __pv_queued_spin_unlock(). This thunk is put together with
|
||||
* __pv_queued_spin_unlock() near the top of the file to make sure
|
||||
* that the callee-save thunk and the real unlock function are close
|
||||
* to each other sharing consecutive instruction cachelines.
|
||||
*/
|
||||
#include <asm/qspinlock_paravirt.h>
|
||||
|
||||
Loading…
Reference in New Issue