drm/msm: update generated headers
Pull in additional regs needed for a430, etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
61965d3d57
commit
a2272e48ee
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@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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Copyright (C) 2013-2015 by the following authors:
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Copyright (C) 2013-2016 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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@ -111,10 +112,14 @@ enum a3xx_vtx_fmt {
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VFMT_8_8_SNORM = 53,
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VFMT_8_8_8_SNORM = 54,
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VFMT_8_8_8_8_SNORM = 55,
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VFMT_10_10_10_2_UINT = 60,
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VFMT_10_10_10_2_UNORM = 61,
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VFMT_10_10_10_2_SINT = 62,
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VFMT_10_10_10_2_SNORM = 63,
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VFMT_10_10_10_2_UINT = 56,
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VFMT_10_10_10_2_UNORM = 57,
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VFMT_10_10_10_2_SINT = 58,
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VFMT_10_10_10_2_SNORM = 59,
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VFMT_2_10_10_10_UINT = 60,
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VFMT_2_10_10_10_UNORM = 61,
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VFMT_2_10_10_10_SINT = 62,
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VFMT_2_10_10_10_SNORM = 63,
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};
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enum a3xx_tex_fmt {
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@ -138,10 +143,12 @@ enum a3xx_tex_fmt {
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TFMT_DXT1 = 36,
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TFMT_DXT3 = 37,
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TFMT_DXT5 = 38,
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TFMT_2_10_10_10_UNORM = 40,
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TFMT_10_10_10_2_UNORM = 41,
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TFMT_9_9_9_E5_FLOAT = 42,
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TFMT_11_11_10_FLOAT = 43,
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TFMT_A8_UNORM = 44,
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TFMT_L8_UNORM = 45,
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TFMT_L8_A8_UNORM = 47,
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TFMT_8_UNORM = 48,
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TFMT_8_8_UNORM = 49,
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@ -183,6 +190,8 @@ enum a3xx_tex_fmt {
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TFMT_32_SINT = 92,
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TFMT_32_32_SINT = 93,
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TFMT_32_32_32_32_SINT = 95,
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TFMT_2_10_10_10_UINT = 96,
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TFMT_10_10_10_2_UINT = 97,
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TFMT_ETC2_RG11_SNORM = 112,
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TFMT_ETC2_RG11_UNORM = 113,
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TFMT_ETC2_R11_SNORM = 114,
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@ -215,6 +224,9 @@ enum a3xx_color_fmt {
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RB_R8_UINT = 14,
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RB_R8_SINT = 15,
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RB_R10G10B10A2_UNORM = 16,
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RB_A2R10G10B10_UNORM = 17,
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RB_R10G10B10A2_UINT = 18,
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RB_A2R10G10B10_UINT = 19,
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RB_A8_UNORM = 20,
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RB_R8_UNORM = 21,
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RB_R16_FLOAT = 24,
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@ -244,30 +256,273 @@ enum a3xx_color_fmt {
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RB_R32G32B32A32_UINT = 59,
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};
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enum a3xx_sp_perfcounter_select {
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SP_FS_CFLOW_INSTRUCTIONS = 12,
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SP_FS_FULL_ALU_INSTRUCTIONS = 14,
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SP0_ICL1_MISSES = 26,
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SP_ALU_ACTIVE_CYCLES = 29,
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enum a3xx_cp_perfcounter_select {
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CP_ALWAYS_COUNT = 0,
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CP_AHB_PFPTRANS_WAIT = 3,
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CP_AHB_NRTTRANS_WAIT = 6,
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CP_CSF_NRT_READ_WAIT = 8,
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CP_CSF_I1_FIFO_FULL = 9,
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CP_CSF_I2_FIFO_FULL = 10,
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CP_CSF_ST_FIFO_FULL = 11,
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CP_RESERVED_12 = 12,
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CP_CSF_RING_ROQ_FULL = 13,
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CP_CSF_I1_ROQ_FULL = 14,
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CP_CSF_I2_ROQ_FULL = 15,
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CP_CSF_ST_ROQ_FULL = 16,
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CP_RESERVED_17 = 17,
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CP_MIU_TAG_MEM_FULL = 18,
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CP_MIU_NRT_WRITE_STALLED = 22,
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CP_MIU_NRT_READ_STALLED = 23,
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CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
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CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
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CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
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CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
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CP_ME_MICRO_RB_STARVED = 30,
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CP_AHB_RBBM_DWORD_SENT = 40,
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CP_ME_BUSY_CLOCKS = 41,
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CP_ME_WAIT_CONTEXT_AVAIL = 42,
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CP_PFP_TYPE0_PACKET = 43,
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CP_PFP_TYPE3_PACKET = 44,
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CP_CSF_RB_WPTR_NEQ_RPTR = 45,
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CP_CSF_I1_SIZE_NEQ_ZERO = 46,
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CP_CSF_I2_SIZE_NEQ_ZERO = 47,
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CP_CSF_RBI1I2_FETCHING = 48,
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};
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enum a3xx_rop_code {
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ROP_CLEAR = 0,
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ROP_NOR = 1,
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ROP_AND_INVERTED = 2,
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ROP_COPY_INVERTED = 3,
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ROP_AND_REVERSE = 4,
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ROP_INVERT = 5,
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ROP_XOR = 6,
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ROP_NAND = 7,
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ROP_AND = 8,
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ROP_EQUIV = 9,
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ROP_NOOP = 10,
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ROP_OR_INVERTED = 11,
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ROP_COPY = 12,
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ROP_OR_REVERSE = 13,
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ROP_OR = 14,
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ROP_SET = 15,
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enum a3xx_gras_tse_perfcounter_select {
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GRAS_TSEPERF_INPUT_PRIM = 0,
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GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
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GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
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GRAS_TSEPERF_CLIPPED_PRIM = 3,
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GRAS_TSEPERF_NEW_PRIM = 4,
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GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
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GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
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GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
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GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
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GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
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GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
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GRAS_TSEPERF_POST_CLIP_PRIM = 11,
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GRAS_TSEPERF_WORKING_CYCLES = 12,
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GRAS_TSEPERF_PC_STARVE = 13,
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GRAS_TSERASPERF_STALL = 14,
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};
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enum a3xx_gras_ras_perfcounter_select {
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GRAS_RASPERF_16X16_TILES = 0,
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GRAS_RASPERF_8X8_TILES = 1,
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GRAS_RASPERF_4X4_TILES = 2,
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GRAS_RASPERF_WORKING_CYCLES = 3,
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GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
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GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
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GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
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};
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enum a3xx_hlsq_perfcounter_select {
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HLSQ_PERF_SP_VS_CONSTANT = 0,
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HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
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HLSQ_PERF_SP_FS_CONSTANT = 2,
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HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
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HLSQ_PERF_TP_STATE = 4,
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HLSQ_PERF_QUADS = 5,
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HLSQ_PERF_PIXELS = 6,
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HLSQ_PERF_VERTICES = 7,
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HLSQ_PERF_FS8_THREADS = 8,
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HLSQ_PERF_FS16_THREADS = 9,
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HLSQ_PERF_FS32_THREADS = 10,
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HLSQ_PERF_VS8_THREADS = 11,
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HLSQ_PERF_VS16_THREADS = 12,
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HLSQ_PERF_SP_VS_DATA_BYTES = 13,
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HLSQ_PERF_SP_FS_DATA_BYTES = 14,
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HLSQ_PERF_ACTIVE_CYCLES = 15,
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HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
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HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
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HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
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HLSQ_PERF_STALL_CYCLES_UCHE = 19,
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HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
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HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
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HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
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HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
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HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
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HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
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HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
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HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
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HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
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};
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enum a3xx_pc_perfcounter_select {
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PC_PCPERF_VISIBILITY_STREAMS = 0,
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PC_PCPERF_TOTAL_INSTANCES = 1,
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PC_PCPERF_PRIMITIVES_PC_VPC = 2,
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PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
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PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
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PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
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PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
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PC_PCPERF_VERTICES_TO_VFD = 7,
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PC_PCPERF_REUSED_VERTICES = 8,
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PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
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PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
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PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
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PC_PCPERF_CYCLES_IS_WORKING = 12,
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};
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enum a3xx_rb_perfcounter_select {
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RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
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RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
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RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
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RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
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RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
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RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
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RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
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RB_RBPERF_RB_MARB_DATA = 7,
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RB_RBPERF_SP_RB_QUAD = 8,
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RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
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RB_RBPERF_GMEM_CH0_READ = 10,
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RB_RBPERF_GMEM_CH1_READ = 11,
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RB_RBPERF_GMEM_CH0_WRITE = 12,
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RB_RBPERF_GMEM_CH1_WRITE = 13,
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RB_RBPERF_CP_CONTEXT_DONE = 14,
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RB_RBPERF_CP_CACHE_FLUSH = 15,
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RB_RBPERF_CP_ZPASS_DONE = 16,
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};
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enum a3xx_rbbm_perfcounter_select {
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RBBM_ALAWYS_ON = 0,
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RBBM_VBIF_BUSY = 1,
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RBBM_TSE_BUSY = 2,
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RBBM_RAS_BUSY = 3,
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RBBM_PC_DCALL_BUSY = 4,
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RBBM_PC_VSD_BUSY = 5,
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RBBM_VFD_BUSY = 6,
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RBBM_VPC_BUSY = 7,
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RBBM_UCHE_BUSY = 8,
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RBBM_VSC_BUSY = 9,
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RBBM_HLSQ_BUSY = 10,
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RBBM_ANY_RB_BUSY = 11,
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RBBM_ANY_TEX_BUSY = 12,
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RBBM_ANY_USP_BUSY = 13,
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RBBM_ANY_MARB_BUSY = 14,
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RBBM_ANY_ARB_BUSY = 15,
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RBBM_AHB_STATUS_BUSY = 16,
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RBBM_AHB_STATUS_STALLED = 17,
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RBBM_AHB_STATUS_TXFR = 18,
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RBBM_AHB_STATUS_TXFR_SPLIT = 19,
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RBBM_AHB_STATUS_TXFR_ERROR = 20,
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RBBM_AHB_STATUS_LONG_STALL = 21,
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RBBM_RBBM_STATUS_MASKED = 22,
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};
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enum a3xx_sp_perfcounter_select {
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SP_LM_LOAD_INSTRUCTIONS = 0,
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SP_LM_STORE_INSTRUCTIONS = 1,
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SP_LM_ATOMICS = 2,
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SP_UCHE_LOAD_INSTRUCTIONS = 3,
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SP_UCHE_STORE_INSTRUCTIONS = 4,
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SP_UCHE_ATOMICS = 5,
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SP_VS_TEX_INSTRUCTIONS = 6,
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SP_VS_CFLOW_INSTRUCTIONS = 7,
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SP_VS_EFU_INSTRUCTIONS = 8,
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SP_VS_FULL_ALU_INSTRUCTIONS = 9,
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SP_VS_HALF_ALU_INSTRUCTIONS = 10,
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SP_FS_TEX_INSTRUCTIONS = 11,
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SP_FS_CFLOW_INSTRUCTIONS = 12,
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SP_FS_EFU_INSTRUCTIONS = 13,
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SP_FS_FULL_ALU_INSTRUCTIONS = 14,
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SP_FS_HALF_ALU_INSTRUCTIONS = 15,
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SP_FS_BARY_INSTRUCTIONS = 16,
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SP_VS_INSTRUCTIONS = 17,
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SP_FS_INSTRUCTIONS = 18,
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SP_ADDR_LOCK_COUNT = 19,
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SP_UCHE_READ_TRANS = 20,
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SP_UCHE_WRITE_TRANS = 21,
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SP_EXPORT_VPC_TRANS = 22,
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SP_EXPORT_RB_TRANS = 23,
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SP_PIXELS_KILLED = 24,
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SP_ICL1_REQUESTS = 25,
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SP_ICL1_MISSES = 26,
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SP_ICL0_REQUESTS = 27,
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SP_ICL0_MISSES = 28,
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SP_ALU_ACTIVE_CYCLES = 29,
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SP_EFU_ACTIVE_CYCLES = 30,
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SP_STALL_CYCLES_BY_VPC = 31,
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SP_STALL_CYCLES_BY_TP = 32,
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SP_STALL_CYCLES_BY_UCHE = 33,
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SP_STALL_CYCLES_BY_RB = 34,
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SP_ACTIVE_CYCLES_ANY = 35,
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SP_ACTIVE_CYCLES_ALL = 36,
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};
|
||||
|
||||
enum a3xx_tp_perfcounter_select {
|
||||
TPL1_TPPERF_L1_REQUESTS = 0,
|
||||
TPL1_TPPERF_TP0_L1_REQUESTS = 1,
|
||||
TPL1_TPPERF_TP0_L1_MISSES = 2,
|
||||
TPL1_TPPERF_TP1_L1_REQUESTS = 3,
|
||||
TPL1_TPPERF_TP1_L1_MISSES = 4,
|
||||
TPL1_TPPERF_TP2_L1_REQUESTS = 5,
|
||||
TPL1_TPPERF_TP2_L1_MISSES = 6,
|
||||
TPL1_TPPERF_TP3_L1_REQUESTS = 7,
|
||||
TPL1_TPPERF_TP3_L1_MISSES = 8,
|
||||
TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
|
||||
TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
|
||||
TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
|
||||
TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
|
||||
TPL1_TPPERF_BILINEAR_OPS = 13,
|
||||
TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
|
||||
TPL1_TPPERF_QUADQUADS_SHADOW = 15,
|
||||
TPL1_TPPERF_QUADS_ARRAY = 16,
|
||||
TPL1_TPPERF_QUADS_PROJECTION = 17,
|
||||
TPL1_TPPERF_QUADS_GRADIENT = 18,
|
||||
TPL1_TPPERF_QUADS_1D2D = 19,
|
||||
TPL1_TPPERF_QUADS_3DCUBE = 20,
|
||||
TPL1_TPPERF_ZERO_LOD = 21,
|
||||
TPL1_TPPERF_OUTPUT_TEXELS = 22,
|
||||
TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
|
||||
TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
|
||||
TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
|
||||
TPL1_TPPERF_LATENCY = 26,
|
||||
TPL1_TPPERF_LATENCY_TRANS = 27,
|
||||
};
|
||||
|
||||
enum a3xx_vfd_perfcounter_select {
|
||||
VFD_PERF_UCHE_BYTE_FETCHED = 0,
|
||||
VFD_PERF_UCHE_TRANS = 1,
|
||||
VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
|
||||
VFD_PERF_FETCH_INSTRUCTIONS = 3,
|
||||
VFD_PERF_DECODE_INSTRUCTIONS = 4,
|
||||
VFD_PERF_ACTIVE_CYCLES = 5,
|
||||
VFD_PERF_STALL_CYCLES_UCHE = 6,
|
||||
VFD_PERF_STALL_CYCLES_HLSQ = 7,
|
||||
VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
|
||||
VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
|
||||
};
|
||||
|
||||
enum a3xx_vpc_perfcounter_select {
|
||||
VPC_PERF_SP_LM_PRIMITIVES = 0,
|
||||
VPC_PERF_COMPONENTS_FROM_SP = 1,
|
||||
VPC_PERF_SP_LM_COMPONENTS = 2,
|
||||
VPC_PERF_ACTIVE_CYCLES = 3,
|
||||
VPC_PERF_STALL_CYCLES_LM = 4,
|
||||
VPC_PERF_STALL_CYCLES_RAS = 5,
|
||||
};
|
||||
|
||||
enum a3xx_uche_perfcounter_select {
|
||||
UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
|
||||
UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
|
||||
UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
|
||||
UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
|
||||
UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
|
||||
UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
|
||||
UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
|
||||
UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
|
||||
UCHE_UCHEPERF_EVICTS = 16,
|
||||
UCHE_UCHEPERF_FLUSHES = 17,
|
||||
UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
|
||||
UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
|
||||
UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
|
||||
};
|
||||
|
||||
enum a3xx_rb_blend_opcode {
|
||||
|
|
@ -1429,15 +1684,23 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
|
|||
#define REG_A3XX_PC_RESTART_INDEX 0x000021ed
|
||||
|
||||
#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
|
||||
#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
|
||||
|
|
@ -1451,17 +1714,39 @@ static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
|
|||
#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
|
||||
|
||||
#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000
|
||||
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
|
||||
#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc
|
||||
#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000
|
||||
#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
|
||||
#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
|
||||
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
|
||||
|
|
@ -1478,13 +1763,13 @@ static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
|
||||
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
|
||||
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
|
||||
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
||||
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
|
||||
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
|
||||
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
|
||||
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
|
||||
{
|
||||
|
|
@ -1498,13 +1783,13 @@ static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
|
||||
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
|
||||
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
|
||||
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
||||
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
|
||||
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
|
||||
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
|
||||
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
|
||||
{
|
||||
|
|
@ -1518,13 +1803,13 @@ static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
|
||||
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
|
||||
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
|
||||
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
|
||||
static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
|
||||
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
|
||||
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
|
||||
static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
|
||||
{
|
||||
|
|
@ -1532,13 +1817,13 @@ static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
|
||||
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
|
||||
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
|
||||
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
|
||||
static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
|
||||
}
|
||||
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
|
||||
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
|
||||
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
|
||||
static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
|
||||
{
|
||||
|
|
@ -1620,12 +1905,24 @@ static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_VFD_CONTROL_1 0x00002241
|
||||
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
|
||||
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f
|
||||
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
|
||||
static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
|
||||
}
|
||||
#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0
|
||||
#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4
|
||||
static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
|
||||
}
|
||||
#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00
|
||||
#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8
|
||||
static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
|
||||
}
|
||||
#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
|
||||
#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
|
||||
static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
|
||||
|
|
@ -2008,24 +2305,19 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffe
|
|||
return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
|
||||
#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008
|
||||
#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
||||
#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
||||
static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
|
||||
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
||||
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
||||
static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
|
||||
#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
|
||||
static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
||||
#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
|
||||
static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
||||
|
|
@ -2033,8 +2325,6 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|||
return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
|
||||
#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
|
||||
#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000
|
||||
#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
|
||||
#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
|
||||
static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
|
||||
|
|
@ -2075,7 +2365,8 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
|
|||
{
|
||||
return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
|
||||
#define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000
|
||||
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000
|
||||
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
|
||||
static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
|
||||
{
|
||||
|
|
@ -2085,24 +2376,26 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
|
|||
static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
|
||||
|
||||
static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
|
||||
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
|
||||
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
|
||||
#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100
|
||||
#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
|
||||
#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
|
||||
static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
|
||||
#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
|
||||
#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
|
||||
static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000
|
||||
#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
|
||||
#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
|
||||
static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
|
||||
|
|
@ -2113,25 +2406,25 @@ static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
|
|||
static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
|
||||
|
||||
static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
||||
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
||||
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
||||
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
||||
{
|
||||
|
|
@ -2139,6 +2432,12 @@ static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
|
||||
#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
|
||||
#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
||||
#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
||||
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
||||
|
|
@ -2155,8 +2454,38 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|||
#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
|
||||
|
||||
#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
|
||||
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
|
||||
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
|
||||
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
|
||||
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
|
||||
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
|
||||
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
|
||||
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
|
||||
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
|
||||
}
|
||||
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
|
||||
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
|
||||
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
|
||||
{
|
||||
return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
|
||||
|
||||
|
|
@ -2182,24 +2511,22 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffe
|
|||
return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
|
||||
#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008
|
||||
#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
||||
#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
||||
static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
|
||||
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
||||
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
||||
static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
|
||||
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
|
||||
static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000
|
||||
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000
|
||||
#define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000
|
||||
#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
||||
#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
|
||||
static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
||||
|
|
@ -2235,7 +2562,7 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
|
|||
{
|
||||
return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
|
||||
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000
|
||||
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
|
||||
static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
|
||||
{
|
||||
|
|
@ -2243,6 +2570,12 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
|
||||
#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
|
||||
#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
||||
#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
||||
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
||||
|
|
@ -2259,8 +2592,38 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|||
#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
|
||||
|
||||
#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
|
||||
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
|
||||
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
|
||||
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
|
||||
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
|
||||
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
|
||||
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
|
||||
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
|
||||
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
|
||||
}
|
||||
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
|
||||
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
|
||||
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
|
||||
{
|
||||
return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
@ -119,6 +120,23 @@ enum adreno_rb_copy_control_mode {
|
|||
RB_COPY_DEPTH_STENCIL = 5,
|
||||
};
|
||||
|
||||
enum a3xx_rop_code {
|
||||
ROP_CLEAR = 0,
|
||||
ROP_NOR = 1,
|
||||
ROP_AND_INVERTED = 2,
|
||||
ROP_COPY_INVERTED = 3,
|
||||
ROP_AND_REVERSE = 4,
|
||||
ROP_INVERT = 5,
|
||||
ROP_NAND = 7,
|
||||
ROP_AND = 8,
|
||||
ROP_EQUIV = 9,
|
||||
ROP_NOOP = 10,
|
||||
ROP_OR_INVERTED = 11,
|
||||
ROP_OR_REVERSE = 13,
|
||||
ROP_OR = 14,
|
||||
ROP_SET = 15,
|
||||
};
|
||||
|
||||
enum a3xx_render_mode {
|
||||
RB_RENDERING_PASS = 0,
|
||||
RB_TILING_PASS = 1,
|
||||
|
|
|
|||
|
|
@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
@ -172,6 +173,11 @@ enum adreno_pm4_type3_packets {
|
|||
CP_UNKNOWN_1A = 26,
|
||||
CP_UNKNOWN_4E = 78,
|
||||
CP_WIDE_REG_WRITE = 116,
|
||||
CP_SCRATCH_TO_REG = 77,
|
||||
CP_REG_TO_SCRATCH = 74,
|
||||
CP_WAIT_MEM_WRITES = 18,
|
||||
CP_COND_REG_EXEC = 71,
|
||||
CP_MEM_TO_REG = 66,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
|
|
@ -199,7 +205,11 @@ enum adreno_state_type {
|
|||
|
||||
enum adreno_state_src {
|
||||
SS_DIRECT = 0,
|
||||
SS_INVALID_ALL_IC = 2,
|
||||
SS_INVALID_PART_IC = 3,
|
||||
SS_INDIRECT = 4,
|
||||
SS_INDIRECT_TCM = 5,
|
||||
SS_INDIRECT_STM = 6,
|
||||
};
|
||||
|
||||
enum a4xx_index_size {
|
||||
|
|
@ -227,7 +237,7 @@ static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
|
|||
{
|
||||
return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000
|
||||
#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
|
||||
#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
|
||||
static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
|
||||
{
|
||||
|
|
@ -499,5 +509,29 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
|||
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
||||
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
||||
static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
|
||||
}
|
||||
#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
|
||||
#define CP_REG_TO_MEM_0_CNT__SHIFT 19
|
||||
static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
|
||||
}
|
||||
#define CP_REG_TO_MEM_0_64B 0x40000000
|
||||
#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
|
||||
|
||||
#define REG_CP_REG_TO_MEM_1 0x00000001
|
||||
#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
|
||||
#define CP_REG_TO_MEM_1_DEST__SHIFT 0
|
||||
static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* ADRENO_PM4_XML */
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -8,11 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-08 08:20:42)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-02-09 03:18:10)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
|
||||
|
|
@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
Loading…
Reference in New Issue