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ASoC: tlv320aic3x: add input clock selection 

This patch adds input selection of main codec clock - from what pin.
Both registers set same value since codec uses clock divider or pll at one time.

Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Jiri Prchal 2012-07-10 14:36:58 +02:00 committed by Mark Brown
parent bb1daa803c
commit a1f34af0ec
2 changed files with 14 additions and 0 deletions
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6
sound/soc/codecs/tlv320aic3x.c
View File

@ -1002,6 +1002,12 @@ static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
struct snd_soc_codec *codec = codec_dai->codec; struct snd_soc_codec *codec = codec_dai->codec;
struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
/* set clock on MCLK or GPIO2 or BCLK */
snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
clk_id << PLLCLK_IN_SHIFT);
snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
clk_id << CLKDIV_IN_SHIFT);
aic3x->sysclk = freq; aic3x->sysclk = freq;
return 0; return 0;
} }

8
sound/soc/codecs/tlv320aic3x.h
View File

@ -195,6 +195,14 @@
#define PLL_CLKIN_SHIFT 4 #define PLL_CLKIN_SHIFT 4
#define MCLK_SOURCE 0x0 #define MCLK_SOURCE 0x0
#define PLL_CLKDIV_SHIFT 0 #define PLL_CLKDIV_SHIFT 0
#define PLLCLK_IN_MASK 0x30
#define PLLCLK_IN_SHIFT 4
#define CLKDIV_IN_MASK 0xc0
#define CLKDIV_IN_SHIFT 6
/* clock in source */
#define CLKIN_MCLK 0
#define CLKIN_GPIO2 1
#define CLKIN_BCLK 2
/* Software reset register bits */ /* Software reset register bits */
#define SOFT_RESET 0x80 #define SOFT_RESET 0x80