ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. This is the last step of clock framework transition for pxa platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and zylonite (pxa3xx). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
This commit is contained in:
Robert Jarzmik
parent
8e3afafe99
commit
a1c0a6adbc
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@ -606,7 +606,7 @@ config ARCH_PXA
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select ARCH_REQUIRE_GPIOLIB
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select ARM_CPU_SUSPEND if PM
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select AUTO_ZRELADDR
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select COMMON_CLK if PXA27x || PXA25x
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select COMMON_CLK
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select CLKSRC_OF
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@ -11,7 +11,7 @@ obj-$(CONFIG_PM) += pm.o sleep.o standby.o
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# SoC-specific code
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obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
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obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_CPU_PXA300) += pxa300.o
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obj-$(CONFIG_CPU_PXA320) += pxa320.o
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obj-$(CONFIG_CPU_PXA930) += pxa930.o
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@ -1,55 +0,0 @@
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/*
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* linux/arch/arm/mach-pxa/clock-pxa2xx.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <mach/pxa2xx-regs.h>
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#include "clock.h"
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void clk_pxa2xx_cken_enable(struct clk *clk)
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{
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CKEN |= 1 << clk->cken;
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}
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void clk_pxa2xx_cken_disable(struct clk *clk)
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{
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CKEN &= ~(1 << clk->cken);
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}
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const struct clkops clk_pxa2xx_cken_ops = {
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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};
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#ifdef CONFIG_PM
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static uint32_t saved_cken;
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static int pxa2xx_clock_suspend(void)
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{
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saved_cken = CKEN;
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return 0;
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}
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static void pxa2xx_clock_resume(void)
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{
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CKEN = saved_cken;
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}
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#else
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#define pxa2xx_clock_suspend NULL
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#define pxa2xx_clock_resume NULL
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#endif
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struct syscore_ops pxa2xx_clock_syscore_ops = {
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.suspend = pxa2xx_clock_suspend,
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.resume = pxa2xx_clock_resume,
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};
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@ -1,212 +0,0 @@
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/*
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* linux/arch/arm/mach-pxa/clock-pxa3xx.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <mach/smemc.h>
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#include <mach/pxa3xx-regs.h>
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/* Ring Oscillator Clock: 60MHz */
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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#define ACCR_PCCE (1 << 11)
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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unsigned long acsr, xclkcfg;
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unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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acsr = ACSR;
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xl = acsr & 0x1f;
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xn = (acsr >> 8) & 0x7;
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hss = (acsr >> 14) & 0x3;
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XL = xl * BASE_CLK;
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XN = xn * XL;
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ro = acsr & ACCR_D0CS;
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
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HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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if (info) {
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pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
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RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
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(ro) ? "" : "in");
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pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
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XL / 1000000, (XL % 1000000) / 10000, xl);
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pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
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XN / 1000000, (XN % 1000000) / 10000, xn,
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(t) ? "" : "in");
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pr_info("HSIO bus clock: %d.%02dMHz\n",
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HSS / 1000000, (HSS % 1000000) / 10000);
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}
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return CLK / 1000;
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}
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/*
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* Return the current AC97 clock frequency.
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*/
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static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
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{
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unsigned long rate = 312000000;
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unsigned long ac97_div;
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ac97_div = AC97_DIV;
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/* This may loose precision for some rates but won't for the
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* standard 24.576MHz.
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*/
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rate /= (ac97_div >> 12) & 0x7fff;
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rate *= (ac97_div & 0xfff);
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return rate;
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}
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/*
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* Return the current HSIO bus clock frequency
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*/
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static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
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{
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unsigned long acsr;
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unsigned int hss, hsio_clk;
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acsr = ACSR;
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hss = (acsr >> 14) & 0x3;
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hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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return hsio_clk;
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}
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
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static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
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{
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unsigned long acsr = ACSR;
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unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
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return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
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df_clkdiv[(memclkcfg >> 16) & 0x3];
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}
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void clk_pxa3xx_cken_enable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA |= mask;
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else if (clk->cken < 64)
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CKENB |= mask;
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else
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CKENC |= mask;
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}
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void clk_pxa3xx_cken_disable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA &= ~mask;
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else if (clk->cken < 64)
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CKENB &= ~mask;
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else
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CKENC &= ~mask;
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}
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const struct clkops clk_pxa3xx_cken_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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};
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const struct clkops clk_pxa3xx_hsio_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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const struct clkops clk_pxa3xx_ac97_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_ac97_getrate,
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};
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const struct clkops clk_pxa3xx_smemc_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_smemc_getrate,
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};
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static void clk_pout_enable(struct clk *clk)
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{
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OSCC |= OSCC_PEN;
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}
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static void clk_pout_disable(struct clk *clk)
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{
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OSCC &= ~OSCC_PEN;
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}
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const struct clkops clk_pxa3xx_pout_ops = {
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.enable = clk_pout_enable,
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.disable = clk_pout_disable,
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};
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#ifdef CONFIG_PM
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static uint32_t cken[2];
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static uint32_t accr;
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static int pxa3xx_clock_suspend(void)
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{
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cken[0] = CKENA;
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cken[1] = CKENB;
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accr = ACCR;
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return 0;
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}
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static void pxa3xx_clock_resume(void)
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{
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ACCR = accr;
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CKENA = cken[0];
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CKENB = cken[1];
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}
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#else
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#define pxa3xx_clock_suspend NULL
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#define pxa3xx_clock_resume NULL
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#endif
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struct syscore_ops pxa3xx_clock_syscore_ops = {
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.suspend = pxa3xx_clock_suspend,
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.resume = pxa3xx_clock_resume,
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};
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@ -1,86 +0,0 @@
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/*
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* linux/arch/arm/mach-sa1100/clock.c
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/clkdev.h>
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#include "clock.h"
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static DEFINE_SPINLOCK(clocks_lock);
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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if (clk->delay)
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udelay(clk->delay);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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WARN_ON(clk->enabled == 0);
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spin_lock_irqsave(&clocks_lock, flags);
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if (--clk->enabled == 0)
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clk->ops->disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long rate;
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rate = clk->rate;
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if (clk->ops->getrate)
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rate = clk->ops->getrate(clk);
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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int ret = -EINVAL;
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if (clk->ops->setrate) {
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spin_lock_irqsave(&clocks_lock, flags);
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ret = clk->ops->setrate(clk, rate);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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void clk_dummy_enable(struct clk *clk)
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{
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}
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void clk_dummy_disable(struct clk *clk)
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{
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}
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const struct clkops clk_dummy_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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};
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struct clk clk_dummy = {
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.ops = &clk_dummy_ops,
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};
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@ -1,80 +0,0 @@
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#include <linux/clkdev.h>
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#include <linux/syscore_ops.h>
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struct clkops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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unsigned long (*getrate)(struct clk *);
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int (*setrate)(struct clk *, unsigned long);
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};
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struct clk {
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const struct clkops *ops;
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unsigned long rate;
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unsigned int cken;
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unsigned int delay;
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unsigned int enabled;
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};
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void clk_dummy_enable(struct clk *);
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void clk_dummy_disable(struct clk *);
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extern const struct clkops clk_dummy_ops;
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extern struct clk clk_dummy;
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#define INIT_CLKREG(_clk,_devname,_conname) \
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{ \
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.clk = _clk, \
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.dev_id = _devname, \
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.con_id = _conname, \
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}
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#define DEFINE_CK(_name, _cken, _ops) \
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struct clk clk_##_name = { \
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.ops = _ops, \
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.cken = CKEN_##_cken, \
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}
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#define DEFINE_CLK(_name, _ops, _rate, _delay) \
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struct clk clk_##_name = { \
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.ops = _ops, \
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.rate = _rate, \
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.delay = _delay, \
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}
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#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \
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struct clk clk_##_name = { \
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.ops = &clk_pxa2xx_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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extern const struct clkops clk_pxa2xx_cken_ops;
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void clk_pxa2xx_cken_enable(struct clk *clk);
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void clk_pxa2xx_cken_disable(struct clk *clk);
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extern struct syscore_ops pxa2xx_clock_syscore_ops;
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#if defined(CONFIG_PXA3xx)
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#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
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struct clk clk_##_name = { \
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.ops = &clk_pxa3xx_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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extern const struct clkops clk_pxa3xx_cken_ops;
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extern const struct clkops clk_pxa3xx_hsio_ops;
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extern const struct clkops clk_pxa3xx_ac97_ops;
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extern const struct clkops clk_pxa3xx_pout_ops;
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extern const struct clkops clk_pxa3xx_smemc_ops;
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extern void clk_pxa3xx_cken_enable(struct clk *);
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extern void clk_pxa3xx_cken_disable(struct clk *);
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extern struct syscore_ops pxa3xx_clock_syscore_ops;
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#endif
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@ -40,7 +40,6 @@
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#include "devices.h"
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#include "generic.h"
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#include "clock.h"
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/* Only e800 has 128MB RAM */
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void __init eseries_fixup(struct tag *tags, char **cmdline)
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@ -67,6 +67,8 @@ void __init pxa_timer_init(void)
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pxa25x_clocks_init();
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if (cpu_is_pxa27x())
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pxa27x_clocks_init();
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if (cpu_is_pxa3xx())
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pxa3xx_clocks_init();
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pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000),
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get_clock_tick_rate());
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}
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@ -39,6 +39,7 @@ extern void __init pxa27x_init_irq(void);
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extern void __init pxa27x_map_io(void);
|
||||
|
||||
#define pxa3xx_handle_irq ichp_handle_irq
|
||||
extern int __init pxa3xx_clocks_init(void);
|
||||
extern void __init pxa3xx_dt_init_irq(void);
|
||||
extern void __init pxa3xx_init_irq(void);
|
||||
extern void __init pxa3xx_map_io(void);
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@
|
|||
#include <mach/smemc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
#include "devices.h"
|
||||
|
||||
static unsigned long lubbock_pin_config[] __initdata = {
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@
|
|||
|
||||
#include "generic.h"
|
||||
#include "devices.h"
|
||||
#include "clock.h"
|
||||
|
||||
/*
|
||||
* Various clock factors driven by the CCCR register.
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
|
||||
#include "generic.h"
|
||||
#include "devices.h"
|
||||
#include "clock.h"
|
||||
|
||||
static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
|
||||
|
||||
|
|
@ -84,32 +83,15 @@ static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
|
|||
MFP_ADDR_END,
|
||||
};
|
||||
|
||||
static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
|
||||
static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
|
||||
|
||||
static struct clk_lookup common_clkregs[] = {
|
||||
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
|
||||
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
|
||||
};
|
||||
|
||||
static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
|
||||
|
||||
static struct clk_lookup pxa310_clkregs[] = {
|
||||
INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
|
||||
};
|
||||
|
||||
static int __init pxa300_init(void)
|
||||
{
|
||||
if (cpu_is_pxa300() || cpu_is_pxa310()) {
|
||||
mfp_init_base(io_p2v(MFPR_BASE));
|
||||
mfp_init_addr(pxa300_mfp_addr_map);
|
||||
clkdev_add_table(ARRAY_AND_SIZE(common_clkregs));
|
||||
}
|
||||
|
||||
if (cpu_is_pxa310()) {
|
||||
if (cpu_is_pxa310())
|
||||
mfp_init_addr(pxa310_mfp_addr_map);
|
||||
clkdev_add_table(ARRAY_AND_SIZE(pxa310_clkregs));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
|
||||
#include "generic.h"
|
||||
#include "devices.h"
|
||||
#include "clock.h"
|
||||
|
||||
static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
|
||||
|
||||
|
|
@ -78,20 +77,11 @@ static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
|
|||
MFP_ADDR_END,
|
||||
};
|
||||
|
||||
static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
|
||||
static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
|
||||
|
||||
static struct clk_lookup pxa320_clkregs[] = {
|
||||
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
|
||||
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
|
||||
};
|
||||
|
||||
static int __init pxa320_init(void)
|
||||
{
|
||||
if (cpu_is_pxa320()) {
|
||||
mfp_init_base(io_p2v(MFPR_BASE));
|
||||
mfp_init_addr(pxa320_mfp_addr_map);
|
||||
clkdev_add_table(ARRAY_AND_SIZE(pxa320_clkregs));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -37,67 +37,11 @@
|
|||
|
||||
#include "generic.h"
|
||||
#include "devices.h"
|
||||
#include "clock.h"
|
||||
|
||||
#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
|
||||
#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
|
||||
|
||||
extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
|
||||
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
|
||||
|
||||
static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
|
||||
static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
|
||||
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
|
||||
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
|
||||
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
|
||||
|
||||
static struct clk_lookup pxa3xx_clkregs[] = {
|
||||
INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
|
||||
/* Power I2C clock is always on */
|
||||
INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
|
||||
INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
|
||||
INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
|
||||
INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
#define ISRAM_START 0x5c000000
|
||||
|
|
@ -476,8 +420,6 @@ static int __init pxa3xx_init(void)
|
|||
*/
|
||||
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
|
||||
|
||||
clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
|
||||
|
||||
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
|
||||
return ret;
|
||||
|
||||
|
|
@ -485,7 +427,6 @@ static int __init pxa3xx_init(void)
|
|||
|
||||
register_syscore_ops(&pxa_irq_syscore_ops);
|
||||
register_syscore_ops(&pxa3xx_mfp_syscore_ops);
|
||||
register_syscore_ops(&pxa3xx_clock_syscore_ops);
|
||||
|
||||
if (of_have_populated_dt())
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@
|
|||
|
||||
#include "generic.h"
|
||||
#include "devices.h"
|
||||
#include "clock.h"
|
||||
|
||||
/* common GPIO definitions */
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,6 @@
|
|||
#include <asm/mach/sharpsl_param.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
#include "devices.h"
|
||||
|
||||
static unsigned long tosa_pin_config[] = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue