[ARM] Kirkwood: clarify PCIe MEM bus/physical address distinction
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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@ -105,7 +105,7 @@ void __init kirkwood_setup_cpu_mbus(void)
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setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
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setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE_MEM, -1);
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TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
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/*
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* Setup window for NAND controller.
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@ -43,6 +43,7 @@
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#define KIRKWOOD_REGS_SIZE SZ_1M
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#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
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/*
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@ -126,7 +126,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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*/
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res[1].name = "PCIe Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
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res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
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res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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panic("Request PCIe Memory resource failed\n");
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