perf, x86: add some IBS macros to perf_event.h
Signed-off-by: Robert Richter <robert.richter@amd.com>
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@ -121,12 +121,14 @@ union cpuid10_edx {
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
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#define IBS_FETCH_CNT 0xFFFF0000ULL
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
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/* IbsOpCtl bits */
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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#define IBS_OP_MAX_CNT 0x0000FFFFULL
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#ifdef CONFIG_PERF_EVENTS
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extern void init_hw_perf_events(void);
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@ -279,7 +279,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
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ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
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ctl |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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}
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@ -319,7 +319,7 @@ static inline void op_amd_start_ibs(void)
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return;
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if (ibs_config.fetch_enabled) {
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val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
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val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
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val |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
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@ -341,7 +341,7 @@ static inline void op_amd_start_ibs(void)
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* avoid underflows.
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*/
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ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
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0xFFFFULL);
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IBS_OP_MAX_CNT);
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}
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if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
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ibs_op_ctl |= IBS_OP_CNT_CTL;
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