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MIPS: BCM63XX: enable pcie for BCM6362 

The PCIe controller is almost the same as the BCM6328 one, with only
the SERDES register being at a different location.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5011/
Acked-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jonas Gorski 2013-03-21 14:03:19 +00:00 committed by Ralf Baechle
parent 08a41d1206
commit a156ba61f0
2 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
View File

@ -1365,7 +1365,8 @@
/*************************************************************************
* _REG relative to RSET_MISC
*************************************************************************/
#define MISC_SERDES_CTRL_REG 0x0
#define MISC_SERDES_CTRL_6328_REG 0x0
#define MISC_SERDES_CTRL_6362_REG 0x4
#define SERDES_PCIE_EN (1 << 0)
#define SERDES_PCIE_EXD_EN (1 << 15)

11
arch/mips/pci/pci-bcm63xx.c
View File

@ -121,11 +121,17 @@ void __iomem *pci_iospace_start;
static void __init bcm63xx_reset_pcie(void)
{
u32 val;
u32 reg;
/* enable SERDES */
val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
if (BCMCPU_IS_6328())
reg = MISC_SERDES_CTRL_6328_REG;
else
reg = MISC_SERDES_CTRL_6362_REG;
val = bcm_misc_readl(reg);
val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
bcm_misc_writel(val, reg);
/* reset the PCIe core */
bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void)
switch (bcm63xx_get_cpu_id()) {
case BCM6328_CPU_ID:
case BCM6362_CPU_ID:
return bcm63xx_register_pcie();
case BCM6348_CPU_ID:
case BCM6358_CPU_ID: