[SPARC] cs4231: Fix SBUS support in this driver.
From: Christopher Zimmermann <madroach@zakweb.de> This patch enables SBus support for the cs4231 sound driver. It is tested on an Ultra2. Capture and playback both work. I experienced lags and crashes using certain threaded players like ogg123 and mp3blaster, while the former is lagging far more. This behavior may be specific to SMP systems. It is reproducable using the dummy sound card driver. Sox works flawlessly. Setting up the calculation of ptr in snd_cs4231_playback_pointer was a bit strange. I got it to work by not incrementing the [pc]_periods_sent counter when starting DMA the first time in cs4231_dma_trigger. Therefore this dummy thing. [ I did some minor cleanups -DaveM ] Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Christopher Zimmermann
David S. Miller
parent
1a3e64aa48
commit
a131430c20
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@ -173,7 +173,7 @@ static cs4231_t *cs4231_list;
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#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
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/* definitions for codec irq status */
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/* definitions for codec irq status - CS4231_IRQ_STATUS */
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#define CS4231_PLAYBACK_IRQ 0x10
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#define CS4231_RECORD_IRQ 0x20
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@ -402,7 +402,7 @@ static void snd_cs4231_outm(cs4231_t *chip, unsigned char reg,
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udelay(100);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
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snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
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#endif
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if (chip->calibrate_mute) {
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chip->image[reg] &= mask;
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@ -425,6 +425,10 @@ static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char val
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timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
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timeout--)
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udelay(100);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
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#endif
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, value, CS4231P(chip, REG));
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mb();
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@ -440,15 +444,12 @@ static void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char valu
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udelay(100);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
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snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
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#endif
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, value, CS4231P(chip, REG));
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chip->image[reg] = value;
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mb();
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#if 0
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printk("codec out - reg 0x%x = 0x%x\n", chip->mce_bit | reg, value);
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#endif
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}
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static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
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@ -462,61 +463,14 @@ static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
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udelay(100);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
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snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg);
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#endif
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
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mb();
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ret = __cs4231_readb(chip, CS4231P(chip, REG));
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#if 0
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printk("codec in - reg 0x%x = 0x%x\n", chip->mce_bit | reg, ret);
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#endif
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return ret;
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}
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#if 0
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static void snd_cs4231_debug(cs4231_t *chip)
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{
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printk("CS4231 REGS: INDEX = 0x%02x ",
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__cs4231_readb(chip, CS4231P(chip, REGSEL)));
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printk(" STATUS = 0x%02x\n",
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__cs4231_readb(chip, CS4231P(chip, STATUS)));
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printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
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printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
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printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
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printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
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printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
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printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
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printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
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printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
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printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
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printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
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printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
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printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
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printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
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printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
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printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
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printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
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printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
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printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
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printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
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printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
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printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
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printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
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printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
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printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
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printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
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printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
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printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
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printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
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printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
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printk(" 0x1e: rec upr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
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printk(" 0x0f: ply lwr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
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printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
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}
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#endif
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/*
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* CS4231 detection / MCE routines
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*/
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@ -528,11 +482,12 @@ static void snd_cs4231_busy_wait(cs4231_t *chip)
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/* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
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for (timeout = 5; timeout > 0; timeout--)
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__cs4231_readb(chip, CS4231P(chip, REGSEL));
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/* end of cleanup sequence */
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for (timeout = 250;
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for (timeout = 500;
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timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
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timeout--)
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udelay(100);
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udelay(1000);
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}
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static void snd_cs4231_mce_up(cs4231_t *chip)
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@ -545,12 +500,12 @@ static void snd_cs4231_mce_up(cs4231_t *chip)
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udelay(100);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printk("mce_up - auto calibration time out (0)\n");
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snd_printdd("mce_up - auto calibration time out (0)\n");
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#endif
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chip->mce_bit |= CS4231_MCE;
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timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
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if (timeout == 0x80)
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snd_printk("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
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snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
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if (!(timeout & CS4231_MCE))
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__cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
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spin_unlock_irqrestore(&chip->lock, flags);
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@ -563,18 +518,15 @@ static void snd_cs4231_mce_down(cs4231_t *chip)
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spin_lock_irqsave(&chip->lock, flags);
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snd_cs4231_busy_wait(chip);
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#if 0
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printk("(1) timeout = %i\n", timeout);
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#endif
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printk("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
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snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
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#endif
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chip->mce_bit &= ~CS4231_MCE;
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timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
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if (timeout == 0x80)
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snd_printk("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
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snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
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if ((timeout & CS4231_MCE) == 0) {
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spin_unlock_irqrestore(&chip->lock, flags);
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return;
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@ -590,9 +542,7 @@ static void snd_cs4231_mce_down(cs4231_t *chip)
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spin_unlock_irqrestore(&chip->lock, flags);
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return;
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}
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#if 0
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printk("(2) timeout = %i, jiffies = %li\n", timeout, jiffies);
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#endif
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/* in 10ms increments, check condition, up to 250ms */
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timeout = 25;
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while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
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@ -604,9 +554,7 @@ static void snd_cs4231_mce_down(cs4231_t *chip)
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msleep(10);
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spin_lock_irqsave(&chip->lock, flags);
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}
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#if 0
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printk("(3) jiffies = %li\n", jiffies);
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#endif
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/* in 10ms increments, check condition, up to 100ms */
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timeout = 10;
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while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
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@ -619,54 +567,58 @@ static void snd_cs4231_mce_down(cs4231_t *chip)
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spin_lock_irqsave(&chip->lock, flags);
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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#if 0
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printk("(4) jiffies = %li\n", jiffies);
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snd_printk("mce_down - exit = 0x%x\n", __cs4231_readb(chip, CS4231P(chip, REGSEL)));
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#endif
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}
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#if 0 /* Unused for now... */
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static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
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{
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switch (format & 0xe0) {
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case CS4231_LINEAR_16:
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case CS4231_LINEAR_16_BIG:
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size >>= 1;
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break;
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case CS4231_ADPCM_16:
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return size >> 2;
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}
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if (format & CS4231_STEREO)
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size >>= 1;
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return size;
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}
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#endif
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#ifdef EBUS_SUPPORT
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static void snd_cs4231_ebus_advance_dma(struct ebus_dma_info *p, snd_pcm_substream_t *substream, unsigned int *periods_sent)
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{
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snd_pcm_runtime_t *runtime = substream->runtime;
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while (1) {
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unsigned int dma_size = snd_pcm_lib_period_bytes(substream);
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unsigned int offset = dma_size * (*periods_sent);
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unsigned int period_size = snd_pcm_lib_period_bytes(substream);
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unsigned int offset = period_size * (*periods_sent);
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if (dma_size >= (1 << 24))
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if (period_size >= (1 << 24))
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BUG();
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if (ebus_dma_request(p, runtime->dma_addr + offset, dma_size))
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if (ebus_dma_request(p, runtime->dma_addr + offset, period_size))
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return;
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#if 0
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printk("ebus_advance: Sent period %u (size[%x] offset[%x])\n",
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(*periods_sent), dma_size, offset);
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#endif
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(*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
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}
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}
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#endif
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static void cs4231_dma_trigger(cs4231_t *chip, unsigned int what, int on)
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#ifdef SBUS_SUPPORT
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static void snd_cs4231_sbus_advance_dma(snd_pcm_substream_t *substream, unsigned int *periods_sent)
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{
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cs4231_t *chip = snd_pcm_substream_chip(substream);
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snd_pcm_runtime_t *runtime = substream->runtime;
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unsigned int period_size = snd_pcm_lib_period_bytes(substream);
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unsigned int offset = period_size * (*periods_sent % runtime->periods);
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if (runtime->period_size > 0xffff + 1)
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BUG();
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switch (substream->stream) {
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case SNDRV_PCM_STREAM_PLAYBACK:
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sbus_writel(runtime->dma_addr + offset, chip->port + APCPNVA);
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sbus_writel(period_size, chip->port + APCPNC);
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break;
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case SNDRV_PCM_STREAM_CAPTURE:
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sbus_writel(runtime->dma_addr + offset, chip->port + APCCNVA);
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sbus_writel(period_size, chip->port + APCCNC);
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break;
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}
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(*periods_sent) = (*periods_sent + 1) % runtime->periods;
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}
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#endif
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static void cs4231_dma_trigger(snd_pcm_substream_t *substream, unsigned int what, int on)
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{
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cs4231_t *chip = snd_pcm_substream_chip(substream);
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#ifdef EBUS_SUPPORT
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if (chip->flags & CS4231_FLAG_EBUS) {
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if (what & CS4231_PLAYBACK_ENABLE) {
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@ -694,6 +646,60 @@ static void cs4231_dma_trigger(cs4231_t *chip, unsigned int what, int on)
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} else {
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#endif
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#ifdef SBUS_SUPPORT
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u32 csr = sbus_readl(chip->port + APCCSR);
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/* I don't know why, but on sbus the period counter must
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* only start counting after the first period is sent.
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* Therefore this dummy thing.
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*/
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unsigned int dummy = 0;
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switch (what) {
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case CS4231_PLAYBACK_ENABLE:
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if (on) {
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csr &= ~APC_XINT_PLAY;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_PPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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snd_cs4231_sbus_advance_dma(substream, &dummy);
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csr |= APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
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APC_XINT_PLAY | APC_XINT_EMPT | APC_XINT_GENL |
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APC_XINT_PENA | APC_PDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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} else {
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csr |= APC_PPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_PDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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}
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break;
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case CS4231_RECORD_ENABLE:
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if (on) {
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csr &= ~APC_XINT_CAPT;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_CPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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snd_cs4231_sbus_advance_dma(substream, &dummy);
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csr |= APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
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APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL |
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APC_CDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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} else {
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csr |= APC_CPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_CDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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}
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break;
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}
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#endif
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#ifdef EBUS_SUPPORT
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}
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@ -725,25 +731,12 @@ static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd)
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}
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}
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#if 0
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printk("TRIGGER: what[%x] on(%d)\n",
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what, (cmd == SNDRV_PCM_TRIGGER_START));
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#endif
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spin_lock_irqsave(&chip->lock, flags);
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if (cmd == SNDRV_PCM_TRIGGER_START) {
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cs4231_dma_trigger(chip, what, 1);
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cs4231_dma_trigger(substream, what, 1);
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chip->image[CS4231_IFACE_CTRL] |= what;
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if (what & CS4231_PLAYBACK_ENABLE) {
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snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, 0xff);
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snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, 0xff);
|
||||
}
|
||||
if (what & CS4231_RECORD_ENABLE) {
|
||||
snd_cs4231_out(chip, CS4231_REC_LWR_CNT, 0xff);
|
||||
snd_cs4231_out(chip, CS4231_REC_UPR_CNT, 0xff);
|
||||
}
|
||||
} else {
|
||||
cs4231_dma_trigger(chip, what, 0);
|
||||
cs4231_dma_trigger(substream, what, 0);
|
||||
chip->image[CS4231_IFACE_CTRL] &= ~what;
|
||||
}
|
||||
snd_cs4231_out(chip, CS4231_IFACE_CTRL,
|
||||
|
|
@ -755,9 +748,7 @@ static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd)
|
|||
result = -EINVAL;
|
||||
break;
|
||||
}
|
||||
#if 0
|
||||
snd_cs4231_debug(chip);
|
||||
#endif
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -790,9 +781,6 @@ static unsigned char snd_cs4231_get_format(cs4231_t *chip, int format, int chann
|
|||
}
|
||||
if (channels > 1)
|
||||
rformat |= CS4231_STEREO;
|
||||
#if 0
|
||||
snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
|
||||
#endif
|
||||
return rformat;
|
||||
}
|
||||
|
||||
|
|
@ -944,7 +932,7 @@ static void snd_cs4231_init(cs4231_t *chip)
|
|||
snd_cs4231_mce_down(chip);
|
||||
|
||||
#ifdef SNDRV_DEBUG_MCE
|
||||
snd_printk("init: (1)\n");
|
||||
snd_printdd("init: (1)\n");
|
||||
#endif
|
||||
snd_cs4231_mce_up(chip);
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
|
|
@ -957,7 +945,7 @@ static void snd_cs4231_init(cs4231_t *chip)
|
|||
snd_cs4231_mce_down(chip);
|
||||
|
||||
#ifdef SNDRV_DEBUG_MCE
|
||||
snd_printk("init: (2)\n");
|
||||
snd_printdd("init: (2)\n");
|
||||
#endif
|
||||
|
||||
snd_cs4231_mce_up(chip);
|
||||
|
|
@ -967,7 +955,7 @@ static void snd_cs4231_init(cs4231_t *chip)
|
|||
snd_cs4231_mce_down(chip);
|
||||
|
||||
#ifdef SNDRV_DEBUG_MCE
|
||||
snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
|
||||
snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
|
||||
#endif
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
|
|
@ -981,7 +969,7 @@ static void snd_cs4231_init(cs4231_t *chip)
|
|||
snd_cs4231_mce_down(chip);
|
||||
|
||||
#ifdef SNDRV_DEBUG_MCE
|
||||
snd_printk("init: (4)\n");
|
||||
snd_printdd("init: (4)\n");
|
||||
#endif
|
||||
|
||||
snd_cs4231_mce_up(chip);
|
||||
|
|
@ -991,7 +979,7 @@ static void snd_cs4231_init(cs4231_t *chip)
|
|||
snd_cs4231_mce_down(chip);
|
||||
|
||||
#ifdef SNDRV_DEBUG_MCE
|
||||
snd_printk("init: (5)\n");
|
||||
snd_printdd("init: (5)\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -1022,6 +1010,7 @@ static int snd_cs4231_open(cs4231_t *chip, unsigned int mode)
|
|||
CS4231_RECORD_IRQ |
|
||||
CS4231_TIMER_IRQ);
|
||||
snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
|
||||
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
chip->mode = mode;
|
||||
|
|
@ -1136,11 +1125,21 @@ static int snd_cs4231_playback_hw_free(snd_pcm_substream_t *substream)
|
|||
static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream)
|
||||
{
|
||||
cs4231_t *chip = snd_pcm_substream_chip(substream);
|
||||
snd_pcm_runtime_t *runtime = substream->runtime;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
|
||||
chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
|
||||
CS4231_PLAYBACK_PIO);
|
||||
|
||||
if (runtime->period_size > 0xffff + 1)
|
||||
BUG();
|
||||
|
||||
snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (runtime->period_size - 1) & 0x00ff);
|
||||
snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (runtime->period_size - 1) >> 8 & 0x00ff);
|
||||
chip->p_periods_sent = 0;
|
||||
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1172,12 +1171,16 @@ static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream)
|
|||
static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream)
|
||||
{
|
||||
cs4231_t *chip = snd_pcm_substream_chip(substream);
|
||||
snd_pcm_runtime_t *runtime = substream->runtime;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
|
||||
CS4231_RECORD_PIO);
|
||||
|
||||
snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (runtime->period_size - 1) & 0x00ff);
|
||||
snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (runtime->period_size - 1) >> 8 & 0x00ff);
|
||||
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1196,53 +1199,61 @@ static void snd_cs4231_overrange(cs4231_t *chip)
|
|||
chip->capture_substream->runtime->overrange++;
|
||||
}
|
||||
|
||||
static void snd_cs4231_generic_interrupt(cs4231_t *chip)
|
||||
static irqreturn_t snd_cs4231_generic_interrupt(cs4231_t *chip)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned char status;
|
||||
|
||||
/*This is IRQ is not raised by the cs4231*/
|
||||
if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
|
||||
return IRQ_NONE;
|
||||
|
||||
status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
|
||||
if (!status)
|
||||
return;
|
||||
|
||||
if (status & CS4231_TIMER_IRQ) {
|
||||
if (chip->timer)
|
||||
snd_timer_interrupt(chip->timer, chip->timer->sticks);
|
||||
}
|
||||
if (status & CS4231_PLAYBACK_IRQ)
|
||||
snd_pcm_period_elapsed(chip->playback_substream);
|
||||
if (status & CS4231_RECORD_IRQ) {
|
||||
|
||||
if (status & CS4231_RECORD_IRQ)
|
||||
snd_cs4231_overrange(chip);
|
||||
snd_pcm_period_elapsed(chip->capture_substream);
|
||||
}
|
||||
|
||||
/* ACK the CS4231 interrupt. */
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef SBUS_SUPPORT
|
||||
static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
cs4231_t *chip = dev_id;
|
||||
u32 csr;
|
||||
|
||||
csr = sbus_readl(chip->port + APCCSR);
|
||||
if (!(csr & (APC_INT_PENDING |
|
||||
APC_PLAY_INT |
|
||||
APC_CAPT_INT |
|
||||
APC_GENL_INT |
|
||||
APC_XINT_PEMP |
|
||||
APC_XINT_CEMP)))
|
||||
return IRQ_NONE;
|
||||
|
||||
/* ACK the APC interrupt. */
|
||||
u32 csr = sbus_readl(chip->port + APCCSR);
|
||||
|
||||
sbus_writel(csr, chip->port + APCCSR);
|
||||
|
||||
snd_cs4231_generic_interrupt(chip);
|
||||
if ((chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) &&
|
||||
(csr & APC_PLAY_INT) &&
|
||||
(csr & APC_XINT_PNVA) &&
|
||||
!(csr & APC_XINT_EMPT)) {
|
||||
snd_cs4231_sbus_advance_dma(chip->playback_substream,
|
||||
&chip->p_periods_sent);
|
||||
snd_pcm_period_elapsed(chip->playback_substream);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
if ((chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) &&
|
||||
(csr & APC_CAPT_INT) &&
|
||||
(csr & APC_XINT_CNVA)) {
|
||||
snd_cs4231_sbus_advance_dma(chip->capture_substream,
|
||||
&chip->c_periods_sent);
|
||||
snd_pcm_period_elapsed(chip->capture_substream);
|
||||
}
|
||||
|
||||
return snd_cs4231_generic_interrupt(chip);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1290,7 +1301,8 @@ static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substr
|
|||
#ifdef EBUS_SUPPORT
|
||||
}
|
||||
#endif
|
||||
ptr += (period_bytes - residue);
|
||||
ptr += period_bytes - residue;
|
||||
|
||||
return bytes_to_frames(substream->runtime, ptr);
|
||||
}
|
||||
|
||||
|
|
@ -1314,7 +1326,7 @@ static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substr
|
|||
#ifdef EBUS_SUPPORT
|
||||
}
|
||||
#endif
|
||||
ptr += (period_bytes - residue);
|
||||
ptr += period_bytes - residue;
|
||||
return bytes_to_frames(substream->runtime, ptr);
|
||||
}
|
||||
|
||||
|
|
@ -1328,9 +1340,6 @@ static int snd_cs4231_probe(cs4231_t *chip)
|
|||
int i, id, vers;
|
||||
unsigned char *ptr;
|
||||
|
||||
#if 0
|
||||
snd_cs4231_debug(chip);
|
||||
#endif
|
||||
id = vers = 0;
|
||||
for (i = 0; i < 50; i++) {
|
||||
mb();
|
||||
|
|
@ -1985,13 +1994,13 @@ static int __init snd_cs4231_sbus_create(snd_card_t *card,
|
|||
chip->port = sbus_ioremap(&sdev->resource[0], 0,
|
||||
chip->regs_size, "cs4231");
|
||||
if (!chip->port) {
|
||||
snd_printk("cs4231-%d: Unable to map chip registers.\n", dev);
|
||||
snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
|
||||
SA_SHIRQ, "cs4231", chip)) {
|
||||
snd_printk("cs4231-%d: Unable to grab SBUS IRQ %s\n",
|
||||
snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n",
|
||||
dev,
|
||||
__irq_itoa(sdev->irqs[0]));
|
||||
snd_cs4231_sbus_free(chip);
|
||||
|
|
@ -2113,29 +2122,29 @@ static int __init snd_cs4231_ebus_create(snd_card_t *card,
|
|||
chip->eb2c.regs = ioremap(edev->resource[2].start, 0x10);
|
||||
if (!chip->port || !chip->eb2p.regs || !chip->eb2c.regs) {
|
||||
snd_cs4231_ebus_free(chip);
|
||||
snd_printk("cs4231-%d: Unable to map chip registers.\n", dev);
|
||||
snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (ebus_dma_register(&chip->eb2c)) {
|
||||
snd_cs4231_ebus_free(chip);
|
||||
snd_printk("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
|
||||
snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
if (ebus_dma_irq_enable(&chip->eb2c, 1)) {
|
||||
snd_cs4231_ebus_free(chip);
|
||||
snd_printk("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
|
||||
snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (ebus_dma_register(&chip->eb2p)) {
|
||||
snd_cs4231_ebus_free(chip);
|
||||
snd_printk("cs4231-%d: Unable to register EBUS play DMA\n", dev);
|
||||
snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
if (ebus_dma_irq_enable(&chip->eb2p, 1)) {
|
||||
snd_cs4231_ebus_free(chip);
|
||||
snd_printk("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
|
||||
snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue