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Blackfin arch: Fix bug - IrDA SIR build failed for BF533. 

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Graf Yang 2009-01-07 23:14:39 +08:00 committed by Bryan Wu
parent 7419a327f6
commit a0dcfb16e6
3 changed files with 13 additions and 6 deletions
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7
arch/blackfin/mach-bf533/include/mach/blackfin.h
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@ -44,6 +44,13 @@
#define BFIN_UART_NR_PORTS 1
#define CH_UART_RX CH_UART0_RX
#define CH_UART_TX CH_UART0_TX
#define IRQ_UART_ERROR IRQ_UART0_ERROR
#define IRQ_UART_RX IRQ_UART0_RX
#define IRQ_UART_TX IRQ_UART0_TX
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */

4
arch/blackfin/mach-bf533/include/mach/dma.h
View File

@ -16,8 +16,8 @@
#define CH_SPORT1_RX 3
#define CH_SPORT1_TX 4
#define CH_SPI 5
#define CH_UART_RX 6
#define CH_UART_TX 7
#define CH_UART0_RX 6
#define CH_UART0_TX 7
#define CH_MEM_STREAM0_DEST 8 /* TX */
#define CH_MEM_STREAM0_SRC 9 /* RX */
#define CH_MEM_STREAM1_DEST 10 /* TX */

8
arch/blackfin/mach-bf533/include/mach/irq.h
View File

@ -90,16 +90,16 @@ Core Emulation **
#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
#define IRQ_UART_ERROR 13 /*UART Error Interrupt */
#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
#define IRQ_RTC 14 /*RTC Interrupt */
#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
#define IRQ_TMR0 23 /*Timer 0 */
#define IRQ_TMR1 24 /*Timer 1 */
#define IRQ_TMR2 25 /*Timer 2 */