PCI x86: always use conf1 to access config space below 256 bytes
Thanks to Loic Prylli <loic@myri.com>, who originally proposed this idea. Always using legacy configuration mechanism for the legacy config space and extended mechanism (mmconf) for the extended config space is a simple and very logical approach. It's supposed to resolve all known mmconf problems. It still allows per-device quirks (tweaking dev->cfg_size). It also allows to get rid of mmconf fallback code. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -22,42 +22,9 @@
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#define MMCONFIG_APER_MIN (2 * 1024*1024)
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#define MMCONFIG_APER_MAX (256 * 1024*1024)
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DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
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/* Indicate if the mmcfg resources have been placed into the resource table. */
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static int __initdata pci_mmcfg_resources_inserted;
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/* K8 systems have some devices (typically in the builtin northbridge)
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that are only accessible using type1
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Normally this can be expressed in the MCFG by not listing them
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and assigning suitable _SEGs, but this isn't implemented in some BIOS.
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Instead try to discover all devices on bus 0 that are unreachable using MM
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and fallback for them. */
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static void __init unreachable_devices(void)
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{
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int i, bus;
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/* Use the max bus number from ACPI here? */
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for (bus = 0; bus < PCI_MMCFG_MAX_CHECK_BUS; bus++) {
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for (i = 0; i < 32; i++) {
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unsigned int devfn = PCI_DEVFN(i, 0);
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u32 val1, val2;
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pci_conf1_read(0, bus, devfn, 0, 4, &val1);
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if (val1 == 0xffffffff)
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continue;
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if (pci_mmcfg_arch_reachable(0, bus, devfn)) {
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raw_pci_ops->read(0, bus, devfn, 0, 4, &val2);
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if (val1 == val2)
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continue;
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}
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set_bit(i + 32 * bus, pci_mmcfg_fallback_slots);
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printk(KERN_NOTICE "PCI: No mmconfig possible on device"
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" %02x:%02x\n", bus, i);
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}
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}
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}
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static const char __init *pci_mmcfg_e7520(void)
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{
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u32 win;
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@ -270,8 +237,6 @@ void __init pci_mmcfg_init(int type)
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return;
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if (pci_mmcfg_arch_init()) {
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if (type == 1)
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unreachable_devices();
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if (known_bridge)
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pci_mmcfg_insert_resources(IORESOURCE_BUSY);
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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@ -30,10 +30,6 @@ static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
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struct acpi_mcfg_allocation *cfg;
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int cfg_num;
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if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
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test_bit(PCI_SLOT(devfn) + 32*bus, pci_mmcfg_fallback_slots))
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return 0;
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for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
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cfg = &pci_mmcfg_config[cfg_num];
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if (cfg->pci_segment == seg &&
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@ -68,13 +64,16 @@ static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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u32 base;
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if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
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*value = -1;
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err: *value = -1;
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return -EINVAL;
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}
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if (reg < 256)
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return pci_conf1_read(seg,bus,devfn,reg,len,value);
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base = get_base_addr(seg, bus, devfn);
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if (!base)
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return pci_conf1_read(seg,bus,devfn,reg,len,value);
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goto err;
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spin_lock_irqsave(&pci_config_lock, flags);
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@ -105,9 +104,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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if ((bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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if (reg < 256)
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return pci_conf1_write(seg,bus,devfn,reg,len,value);
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base = get_base_addr(seg, bus, devfn);
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if (!base)
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return pci_conf1_write(seg,bus,devfn,reg,len,value);
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return -EINVAL;
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spin_lock_irqsave(&pci_config_lock, flags);
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@ -134,12 +136,6 @@ static struct pci_raw_ops pci_mmcfg = {
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.write = pci_mmcfg_write,
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};
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int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
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unsigned int devfn)
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{
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return get_base_addr(seg, bus, devfn) != 0;
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}
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int __init pci_mmcfg_arch_init(void)
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{
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printk(KERN_INFO "PCI: Using MMCONFIG\n");
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@ -40,9 +40,7 @@ static char __iomem *get_virt(unsigned int seg, unsigned bus)
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static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
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{
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char __iomem *addr;
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if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
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test_bit(32*bus + PCI_SLOT(devfn), pci_mmcfg_fallback_slots))
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return NULL;
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addr = get_virt(seg, bus);
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if (!addr)
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return NULL;
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@ -56,13 +54,16 @@ static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
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*value = -1;
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err: *value = -1;
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return -EINVAL;
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}
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if (reg < 256)
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return pci_conf1_read(seg,bus,devfn,reg,len,value);
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr)
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return pci_conf1_read(seg,bus,devfn,reg,len,value);
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goto err;
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switch (len) {
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case 1:
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@ -88,9 +89,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
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return -EINVAL;
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if (reg < 256)
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return pci_conf1_write(seg,bus,devfn,reg,len,value);
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr)
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return pci_conf1_write(seg,bus,devfn,reg,len,value);
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return -EINVAL;
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switch (len) {
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case 1:
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@ -126,12 +130,6 @@ static void __iomem * __init mcfg_ioremap(struct acpi_mcfg_allocation *cfg)
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return addr;
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}
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int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
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unsigned int devfn)
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{
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return pci_dev_base(seg, bus, devfn) != NULL;
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}
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int __init pci_mmcfg_arch_init(void)
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{
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int i;
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@ -98,13 +98,6 @@ extern void pcibios_sort(void);
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/* pci-mmconfig.c */
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/* Verify the first 16 busses. We assume that systems with more busses
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get MCFG right. */
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#define PCI_MMCFG_MAX_CHECK_BUS 16
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extern DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
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extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
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unsigned int devfn);
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extern int __init pci_mmcfg_arch_init(void);
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/*
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