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Blackfin arch: remove useless CONFIG_IRQCHIP_DEMUX_GPIO 

since we have this always turned on now and dont want it off (and hasnt been an option in a while)

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Mike Frysinger 2007-11-15 21:12:32 +08:00 committed by Bryan Wu
parent 0feea17f94
commit a055b2b4de
12 changed files with 20 additions and 74 deletions
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5
arch/blackfin/Kconfig
View File

@ -65,11 +65,6 @@ config GENERIC_CALIBRATE_DELAY
bool bool
default y default y
config IRQCHIP_DEMUX_GPIO
bool
depends on (BF52x || BF53x || BF561 || BF54x)
default y
source "init/Kconfig" source "init/Kconfig"
source "kernel/Kconfig.preempt" source "kernel/Kconfig.preempt"

4
arch/blackfin/mach-bf533/boards/H8606.c
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@ -94,10 +94,6 @@ static struct resource smc91x_resources[] = {
.end = IRQ_PROG_INTB, .end = IRQ_PROG_INTB,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
}, { }, {
/*
* denotes the flag pin and is used directly if
* CONFIG_IRQCHIP_DEMUX_GPIO is defined.
*/
.start = IRQ_PF7, .start = IRQ_PF7,
.end = IRQ_PF7, .end = IRQ_PF7,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,

4
arch/blackfin/mach-bf533/boards/generic_board.c
View File

@ -58,10 +58,6 @@ static struct resource smc91x_resources[] = {
.end = IRQ_PROG_INTB, .end = IRQ_PROG_INTB,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
}, { }, {
/*
* denotes the flag pin and is used directly if
* CONFIG_IRQCHIP_DEMUX_GPIO is defined.
*/
.start = IRQ_PF7, .start = IRQ_PF7,
.end = IRQ_PF7, .end = IRQ_PF7,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,

4
arch/blackfin/mach-bf561/boards/generic_board.c
View File

@ -48,10 +48,6 @@ static struct resource smc91x_resources[] = {
.end = IRQ_PROG_INTB, .end = IRQ_PROG_INTB,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
}, { }, {
/*
* denotes the flag pin and is used directly if
* CONFIG_IRQCHIP_DEMUX_GPIO is defined.
*/
.start = IRQ_PF9, .start = IRQ_PF9,
.end = IRQ_PF9, .end = IRQ_PF9,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,

4
arch/blackfin/mach-bf561/boards/tepla.c
View File

@ -31,10 +31,6 @@ static struct resource smc91x_resources[] = {
.end = IRQ_PROG_INTB, .end = IRQ_PROG_INTB,
.flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
}, { }, {
/*
* denotes the flag pin and is used directly if
* CONFIG_IRQCHIP_DEMUX_GPIO is defined.
*/
.start = IRQ_PF7, .start = IRQ_PF7,
.end = IRQ_PF7, .end = IRQ_PF7,
.flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,

25
arch/blackfin/mach-common/ints-priority-dc.c
View File

@ -181,7 +181,6 @@ static struct irq_chip bf561_internal_irqchip = {
.unmask = bf561_internal_unmask_irq, .unmask = bf561_internal_unmask_irq,
}; };
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@ -362,8 +361,6 @@ static void bf561_demux_gpio_irq(unsigned int inta_irq,
} }
#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
void __init init_exception_vectors(void) void __init init_exception_vectors(void)
{ {
SSYNC(); SSYNC();
@ -413,26 +410,21 @@ int __init init_arch_irq(void)
set_irq_chip(irq, &bf561_core_irqchip); set_irq_chip(irq, &bf561_core_irqchip);
else else
set_irq_chip(irq, &bf561_internal_irqchip); set_irq_chip(irq, &bf561_internal_irqchip);
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
if ((irq != IRQ_PROG0_INTA) &&
(irq != IRQ_PROG1_INTA) && (irq != IRQ_PROG2_INTA)) {
#endif
set_irq_handler(irq, handle_simple_irq);
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
} else {
set_irq_chained_handler(irq, bf561_demux_gpio_irq);
}
#endif
if ((irq != IRQ_PROG0_INTA) &&
(irq != IRQ_PROG1_INTA) &&
(irq != IRQ_PROG2_INTA))
set_irq_handler(irq, handle_simple_irq);
else
set_irq_chained_handler(irq, bf561_demux_gpio_irq);
} }
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) { for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
set_irq_chip(irq, &bf561_gpio_irqchip); set_irq_chip(irq, &bf561_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */ /* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq); set_irq_handler(irq, handle_level_irq);
} }
#endif
bfin_write_IMASK(0); bfin_write_IMASK(0);
CSYNC(); CSYNC();
ilat = bfin_read_ILAT(); ilat = bfin_read_ILAT();
@ -457,9 +449,8 @@ int __init init_arch_irq(void)
} }
#ifdef CONFIG_DO_IRQ_L1 #ifdef CONFIG_DO_IRQ_L1
void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text)); __attribute__((l1_text))
#endif #endif
void do_irq(int vec, struct pt_regs *fp) void do_irq(int vec, struct pt_regs *fp)
{ {
if (vec == EVT_IVTMR_P) { if (vec == EVT_IVTMR_P) {

28
arch/blackfin/mach-common/ints-priority-sc.c
View File

@ -308,7 +308,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
} }
#endif /* BF537_GENERIC_ERROR_INT_DEMUX */ #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x) #if !defined(CONFIG_BF54x)
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@ -464,7 +464,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
} }
} }
#else /* CONFIG_IRQCHIP_DEMUX_GPIO */ #else /* CONFIG_BF54x */
#define NR_PINT_SYS_IRQS 4 #define NR_PINT_SYS_IRQS 4
#define NR_PINT_BITS 32 #define NR_PINT_BITS 32
@ -726,7 +726,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
} }
} }
#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ #endif
void __init init_exception_vectors(void) void __init init_exception_vectors(void)
{ {
@ -766,10 +766,10 @@ int __init init_arch_irq(void)
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL); bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
#ifdef CONFIG_BF54x # ifdef CONFIG_BF54x
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
bfin_write_SIC_IWR2(IWR_ENABLE_ALL); bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
#endif # endif
#else #else
bfin_write_SIC_IMASK(SIC_UNMASK_ALL); bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
bfin_write_SIC_IWR(IWR_ENABLE_ALL); bfin_write_SIC_IWR(IWR_ENABLE_ALL);
@ -778,13 +778,13 @@ int __init init_arch_irq(void)
local_irq_disable(); local_irq_disable();
#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x) #ifdef CONFIG_BF54x
#ifdef CONFIG_PINTx_REASSIGN # ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN; pint[0]->assign = CONFIG_PINT0_ASSIGN;
pint[1]->assign = CONFIG_PINT1_ASSIGN; pint[1]->assign = CONFIG_PINT1_ASSIGN;
pint[2]->assign = CONFIG_PINT2_ASSIGN; pint[2]->assign = CONFIG_PINT2_ASSIGN;
pint[3]->assign = CONFIG_PINT3_ASSIGN; pint[3]->assign = CONFIG_PINT3_ASSIGN;
#endif # endif
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
init_pint_lut(); init_pint_lut();
#endif #endif
@ -799,18 +799,17 @@ int __init init_arch_irq(void)
#endif #endif
switch (irq) { switch (irq) {
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#if defined(CONFIG_BF53x) #if defined(CONFIG_BF53x)
case IRQ_PROG_INTA: case IRQ_PROG_INTA:
set_irq_chained_handler(irq, set_irq_chained_handler(irq,
bfin_demux_gpio_irq); bfin_demux_gpio_irq);
break; break;
#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
case IRQ_MAC_RX: case IRQ_MAC_RX:
set_irq_chained_handler(irq, set_irq_chained_handler(irq,
bfin_demux_gpio_irq); bfin_demux_gpio_irq);
break; break;
#endif # endif
#elif defined(CONFIG_BF54x) #elif defined(CONFIG_BF54x)
case IRQ_PINT0: case IRQ_PINT0:
set_irq_chained_handler(irq, set_irq_chained_handler(irq,
@ -841,7 +840,6 @@ int __init init_arch_irq(void)
set_irq_chained_handler(irq, set_irq_chained_handler(irq,
bfin_demux_gpio_irq); bfin_demux_gpio_irq);
break; break;
#endif
#endif #endif
default: default:
set_irq_handler(irq, handle_simple_irq); set_irq_handler(irq, handle_simple_irq);
@ -861,7 +859,6 @@ int __init init_arch_irq(void)
} }
#endif #endif
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#ifndef CONFIG_BF54x #ifndef CONFIG_BF54x
for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
#else #else
@ -871,7 +868,7 @@ int __init init_arch_irq(void)
/* if configured as edge, then will be changed to do_edge_IRQ */ /* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq); set_irq_handler(irq, handle_level_irq);
} }
#endif
bfin_write_IMASK(0); bfin_write_IMASK(0);
CSYNC(); CSYNC();
ilat = bfin_read_ILAT(); ilat = bfin_read_ILAT();
@ -896,9 +893,8 @@ int __init init_arch_irq(void)
} }
#ifdef CONFIG_DO_IRQ_L1 #ifdef CONFIG_DO_IRQ_L1
void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text)); __attribute__((l1_text))
#endif #endif
void do_irq(int vec, struct pt_regs *fp) void do_irq(int vec, struct pt_regs *fp)
{ {
if (vec == EVT_IVTMR_P) { if (vec == EVT_IVTMR_P) {

4
include/asm-blackfin/mach-bf527/irq.h
View File

@ -176,11 +176,7 @@
#define GPIO_IRQ_BASE IRQ_PF0 #define GPIO_IRQ_BASE IRQ_PF0
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PH15+1) #define NR_IRQS (IRQ_PH15+1)
#else
#define NR_IRQS (SYS_IRQS+1)
#endif
#define IVG7 7 #define IVG7 7
#define IVG8 8 #define IVG8 8

4
include/asm-blackfin/mach-bf533/irq.h
View File

@ -130,11 +130,7 @@ Core Emulation **
#define GPIO_IRQ_BASE IRQ_PF0 #define GPIO_IRQ_BASE IRQ_PF0
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PF15+1) #define NR_IRQS (IRQ_PF15+1)
#else
#define NR_IRQS SYS_IRQS
#endif
#define IVG7 7 #define IVG7 7
#define IVG8 8 #define IVG8 8

4
include/asm-blackfin/mach-bf537/irq.h
View File

@ -162,11 +162,7 @@ Core Emulation **
#define GPIO_IRQ_BASE IRQ_PF0 #define GPIO_IRQ_BASE IRQ_PF0
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PH15+1) #define NR_IRQS (IRQ_PH15+1)
#else
#define NR_IRQS (IRQ_UART1_ERROR+1)
#endif
#define IVG7 7 #define IVG7 7
#define IVG8 8 #define IVG8 8

4
include/asm-blackfin/mach-bf548/irq.h
View File

@ -338,11 +338,7 @@ Events (highest priority) EMU 0
#define GPIO_IRQ_BASE IRQ_PA0 #define GPIO_IRQ_BASE IRQ_PA0
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PJ15+1) #define NR_IRQS (IRQ_PJ15+1)
#else
#define NR_IRQS (SYS_IRQS+1)
#endif
/* For compatibility reasons with existing code */ /* For compatibility reasons with existing code */

4
include/asm-blackfin/mach-bf561/irq.h
View File

@ -291,11 +291,7 @@
#define GPIO_IRQ_BASE IRQ_PF0 #define GPIO_IRQ_BASE IRQ_PF0
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PF47 + 1) #define NR_IRQS (IRQ_PF47 + 1)
#else
#define NR_IRQS SYS_IRQS
#endif
#define IVG7 7 #define IVG7 7
#define IVG8 8 #define IVG8 8