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drm/nouveau/vp/nv84: initial vp2 engine implementation 

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ilia Mirkin 2013-06-27 14:12:46 +10:00 committed by Ben Skeggs
parent 44b1e3bd6a
commit a0376b1481
4 changed files with 17 additions and 14 deletions
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2
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
View File

@ -56,6 +56,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
switch (nv_engidx(object->engine)) { switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0; case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0020; break; case NVDEV_ENGINE_GR : addr = 0x0020; break;
case NVDEV_ENGINE_VP : addr = 0x0040; break;
case NVDEV_ENGINE_MPEG : addr = 0x0060; break; case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break; case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
case NVDEV_ENGINE_COPY0: addr = 0x00c0; break; case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
@ -89,6 +90,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
switch (nv_engidx(object->engine)) { switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0; case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break; case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break; case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;

27
drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
View File

@ -19,24 +19,19 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE. * OTHER DEALINGS IN THE SOFTWARE.
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs, Ilia Mirkin
*/ */
#include <core/engctx.h> #include <engine/xtensa.h>
#include <core/class.h>
#include <engine/vp.h> #include <engine/vp.h>
struct nv84_vp_priv {
struct nouveau_engine base;
};
/******************************************************************************* /*******************************************************************************
* VP object classes * VP object classes
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nv84_vp_sclass[] = { nv84_vp_sclass[] = {
{ 0x7476, &nouveau_object_ofuncs },
{}, {},
}; };
@ -48,7 +43,7 @@ static struct nouveau_oclass
nv84_vp_cclass = { nv84_vp_cclass = {
.handle = NV_ENGCTX(VP, 0x84), .handle = NV_ENGCTX(VP, 0x84),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_engctx_ctor, .ctor = _nouveau_xtensa_engctx_ctor,
.dtor = _nouveau_engctx_dtor, .dtor = _nouveau_engctx_dtor,
.init = _nouveau_engctx_init, .init = _nouveau_engctx_init,
.fini = _nouveau_engctx_fini, .fini = _nouveau_engctx_fini,
@ -66,10 +61,10 @@ nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nouveau_object **pobject)
{ {
struct nv84_vp_priv *priv; struct nouveau_xtensa *priv;
int ret; int ret;
ret = nouveau_engine_create(parent, engine, oclass, true, ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true,
"PVP", "vp", &priv); "PVP", "vp", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
@ -78,6 +73,8 @@ nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->unit = 0x01020000; nv_subdev(priv)->unit = 0x01020000;
nv_engine(priv)->cclass = &nv84_vp_cclass; nv_engine(priv)->cclass = &nv84_vp_cclass;
nv_engine(priv)->sclass = nv84_vp_sclass; nv_engine(priv)->sclass = nv84_vp_sclass;
priv->fifo_val = 0x111;
priv->unkd28 = 0x9c544;
return 0; return 0;
} }
@ -86,8 +83,10 @@ nv84_vp_oclass = {
.handle = NV_ENGINE(VP, 0x84), .handle = NV_ENGINE(VP, 0x84),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv84_vp_ctor, .ctor = nv84_vp_ctor,
.dtor = _nouveau_engine_dtor, .dtor = _nouveau_xtensa_dtor,
.init = _nouveau_engine_init, .init = _nouveau_xtensa_init,
.fini = _nouveau_engine_fini, .fini = _nouveau_xtensa_fini,
.rd32 = _nouveau_xtensa_rd32,
.wr32 = _nouveau_xtensa_wr32,
}, },
}; };

1
drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
View File

@ -35,6 +35,7 @@ nv50_mc_intr[] = {
{ 0x00001000, NVDEV_ENGINE_GR }, { 0x00001000, NVDEV_ENGINE_GR },
{ 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84- */ { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84- */
{ 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */ { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */
{ 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */
{ 0x00100000, NVDEV_SUBDEV_TIMER }, { 0x00100000, NVDEV_SUBDEV_TIMER },
{ 0x00200000, NVDEV_SUBDEV_GPIO }, { 0x00200000, NVDEV_SUBDEV_GPIO },
{ 0x04000000, NVDEV_ENGINE_DISP }, { 0x04000000, NVDEV_ENGINE_DISP },

1
drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
View File

@ -172,6 +172,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
switch (i) { switch (i) {
case NVDEV_ENGINE_GR : vme = 0x00; break; case NVDEV_ENGINE_GR : vme = 0x00; break;
case NVDEV_ENGINE_VP : vme = 0x01; break;
case NVDEV_SUBDEV_BAR : vme = 0x06; break; case NVDEV_SUBDEV_BAR : vme = 0x06; break;
case NVDEV_ENGINE_MPEG : vme = 0x08; break; case NVDEV_ENGINE_MPEG : vme = 0x08; break;
case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;