clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq
This is the initial stage to transfer the pxa25x and pxa27x CPU clocks
handling from cpufreq to the clock API. More precisely, the clocks
transferred are :
- cpll : core pll, known also as the CPU core turbo frequency
- core : core, known also as the CPU actual frequency, being either the
CPU core turbo frequency or the CPU core run frequency
This transfer is a prequel to shrink the code in pxa2xx-cpufreq.c, so
that it can become, at least in devicetree builds, the casual cpufreq-dt
driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Robert Jarzmik
Stephen Boyd
parent
3bd31cdc4a
commit
9fe6942950
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@ -18,6 +18,26 @@
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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#define KHz 1000
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#define MHz (1000 * 1000)
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#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
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#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
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#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
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#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
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#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
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#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
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#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
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#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
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#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
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#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
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#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
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#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
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#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
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#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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DEFINE_SPINLOCK(lock);
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static struct clk *pxa_clocks[CLK_MAX];
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@ -106,3 +126,122 @@ void __init clk_pxa_dt_common_init(struct device_node *np)
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{
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of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
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}
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void pxa2xx_core_turbo_switch(bool on)
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{
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unsigned long flags;
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unsigned int unused, clkcfg;
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local_irq_save(flags);
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asm("mrc p14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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clkcfg &= ~CLKCFG_TURBO & ~CLKCFG_HALFTURBO;
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if (on)
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clkcfg |= CLKCFG_TURBO;
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clkcfg |= CLKCFG_FCS;
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asm volatile(
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" b 2f\n"
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" .align 5\n"
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"1: mcr p14, 0, %1, c6, c0, 0\n"
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" b 3f\n"
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"2: b 1b\n"
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"3: nop\n"
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: "=&r" (unused)
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: "r" (clkcfg)
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: );
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local_irq_restore(flags);
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}
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void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
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u32 (*mdrefr_dri)(unsigned int), u32 *mdrefr, u32 *cccr)
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{
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unsigned int clkcfg = freq->clkcfg;
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unsigned int unused, preset_mdrefr, postset_mdrefr;
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unsigned long flags;
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local_irq_save(flags);
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/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
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* we need to preset the smaller DRI before the change. If we're
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* speeding up we need to set the larger DRI value after the change.
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*/
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preset_mdrefr = postset_mdrefr = readl(mdrefr);
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if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
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preset_mdrefr |= mdrefr_dri(freq->membus_khz);
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}
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postset_mdrefr =
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(postset_mdrefr & ~MDREFR_DRI_MASK) |
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mdrefr_dri(freq->membus_khz);
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/* If we're dividing the memory clock by two for the SDRAM clock, this
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* must be set prior to the change. Clearing the divide must be done
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* after the change.
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*/
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if (freq->div2) {
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preset_mdrefr |= MDREFR_DB2_MASK;
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postset_mdrefr |= MDREFR_DB2_MASK;
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} else {
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postset_mdrefr &= ~MDREFR_DB2_MASK;
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}
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/* Set new the CCCR and prepare CLKCFG */
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writel(freq->cccr, cccr);
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asm volatile(
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" ldr r4, [%1]\n"
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" b 2f\n"
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" .align 5\n"
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"1: str %3, [%1] /* preset the MDREFR */\n"
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" mcr p14, 0, %2, c6, c0, 0 /* set CLKCFG[FCS] */\n"
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" str %4, [%1] /* postset the MDREFR */\n"
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" b 3f\n"
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"2: b 1b\n"
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"3: nop\n"
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: "=&r" (unused)
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: "r" (mdrefr), "r" (clkcfg), "r" (preset_mdrefr),
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"r" (postset_mdrefr)
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: "r4", "r5");
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local_irq_restore(flags);
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}
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int pxa2xx_determine_rate(struct clk_rate_request *req,
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struct pxa2xx_freq *freqs, int nb_freqs)
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{
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int i, closest_below = -1, closest_above = -1, ret = 0;
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unsigned long rate;
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for (i = 0; i < nb_freqs; i++) {
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rate = freqs[i].cpll;
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if (rate == req->rate)
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break;
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if (rate < req->min_rate)
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continue;
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if (rate > req->max_rate)
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continue;
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if (rate <= req->rate)
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closest_below = i;
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if ((rate >= req->rate) && (closest_above == -1))
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closest_above = i;
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}
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req->best_parent_hw = NULL;
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if (i < nb_freqs)
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ret = 0;
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else if (closest_below >= 0)
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rate = freqs[closest_below].cpll;
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else if (closest_above >= 0)
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rate = freqs[closest_above].cpll;
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else
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ret = -EINVAL;
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pr_debug("%s(rate=%lu) rate=%lu: %d\n", __func__, req->rate, rate, ret);
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if (!rate)
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req->rate = rate;
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return ret;
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}
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@ -13,6 +13,11 @@
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#ifndef _CLK_PXA_
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#define _CLK_PXA_
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#define CLKCFG_TURBO 0x1
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#define CLKCFG_FCS 0x2
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#define CLKCFG_HALFTURBO 0x4
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#define CLKCFG_FASTBUS 0x8
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#define PARENTS(name) \
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static const char *const name ## _parents[] __initconst
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#define MUX_RO_RATE_RO_OPS(name, clk_name) \
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@ -37,7 +42,7 @@
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#define RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _rate_ops = { \
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static const struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk * __init clk_register_ ## name(void) \
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@ -50,6 +55,41 @@
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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#define RATE_OPS(name, clk_name) \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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.set_rate = name ## _set_rate, \
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.determine_rate = name ## _determine_rate, \
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}; \
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static struct clk * __init clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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NULL, NULL, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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#define MUX_OPS(name, clk_name, flags) \
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static struct clk_hw name ## _mux_hw; \
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static const struct clk_ops name ## _mux_ops = { \
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.get_parent = name ## _get_parent, \
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.set_parent = name ## _set_parent, \
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.determine_rate = name ## _determine_rate, \
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}; \
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static struct clk * __init clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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&name ## _mux_hw, &name ## _mux_ops, \
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NULL, NULL, \
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NULL, NULL, \
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CLK_GET_RATE_NOCACHE | flags); \
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}
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/*
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* CKEN clock type
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* This clock takes it source from 2 possible parents :
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@ -95,6 +135,14 @@ struct desc_clk_cken {
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PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
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NULL, cken_reg, cken_bit, flag)
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struct pxa2xx_freq {
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unsigned long cpll;
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unsigned int membus_khz;
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unsigned int cccr;
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unsigned int div2;
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unsigned int clkcfg;
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};
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static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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return 0;
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@ -105,4 +153,11 @@ extern void clkdev_pxa_register(int ckid, const char *con_id,
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extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
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void clk_pxa_dt_common_init(struct device_node *np);
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void pxa2xx_core_turbo_switch(bool on);
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void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
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u32 (*mdrefr_dri)(unsigned int), u32 *mdrefr,
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u32 *cccr);
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int pxa2xx_determine_rate(struct clk_rate_request *req,
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struct pxa2xx_freq *freqs, int nb_freqs);
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#endif
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@ -18,6 +18,7 @@
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#include <linux/io.h>
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#include <linux/of.h>
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#include <mach/pxa2xx-regs.h>
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#include <mach/smemc.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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@ -30,6 +31,17 @@ enum {
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PXA_CORE_TURBO,
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};
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#define PXA25x_CLKCFG(T) \
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(CLKCFG_FCS | \
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((T) ? CLKCFG_TURBO : 0))
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#define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
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#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
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#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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/*
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* Various clock factors driven by the CCCR register.
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*/
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@ -48,6 +60,34 @@ static const char * const get_freq_khz[] = {
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"core", "run", "cpll", "memory"
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};
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static int get_sdram_rows(void)
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{
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static int sdram_rows;
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unsigned int drac2 = 0, drac0 = 0;
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u32 mdcnfg;
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if (sdram_rows)
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return sdram_rows;
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mdcnfg = readl_relaxed(MDCNFG);
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if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
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drac2 = MDCNFG_DRAC2(mdcnfg);
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if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
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drac0 = MDCNFG_DRAC0(mdcnfg);
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sdram_rows = 1 << (11 + max(drac0, drac2));
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return sdram_rows;
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}
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static u32 mdrefr_dri(unsigned int freq_khz)
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{
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u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
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return interval / 32;
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}
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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@ -139,6 +179,21 @@ static struct desc_clk_cken pxa25x_clocks[] __initdata = {
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clk_pxa25x_memory_parents, 0),
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};
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/*
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* In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
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* - freq_cpll = n * m * L * 3.6864 MHz
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* - n = N2 / 2
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* - m = 2^(M - 1), where 1 <= M <= 3
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* - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
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*/
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static struct pxa2xx_freq pxa25x_freqs[] = {
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/* CPU MEMBUS CCCR DIV2 CCLKCFG */
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{ 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
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{199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
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{298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
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{398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
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};
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static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
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{
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unsigned long clkcfg;
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@ -151,13 +206,24 @@ static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
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return PXA_CORE_RUN;
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}
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static unsigned long clk_pxa25x_core_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
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{
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return parent_rate;
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if (index > PXA_CORE_TURBO)
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return -EINVAL;
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pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
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return 0;
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}
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static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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return __clk_mux_determine_rate(hw, req);
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}
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PARENTS(clk_pxa25x_core) = { "run", "cpll" };
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MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core");
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MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
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static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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@ -184,8 +250,33 @@ static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
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return m * l * n2 * parent_rate / 2;
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}
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static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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return pxa2xx_determine_rate(req, pxa25x_freqs,
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ARRAY_SIZE(pxa25x_freqs));
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}
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static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int i;
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pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
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for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
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if (pxa25x_freqs[i].cpll == rate)
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break;
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if (i >= ARRAY_SIZE(pxa25x_freqs))
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return -EINVAL;
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pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR);
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return 0;
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}
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PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
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RATE_RO_OPS(clk_pxa25x_cpll, "cpll");
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RATE_OPS(clk_pxa25x_cpll, "cpll");
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static void __init pxa25x_register_core(void)
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{
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@ -17,6 +17,8 @@
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <mach/smemc.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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@ -45,11 +47,52 @@ enum {
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PXA_MEM_RUN,
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};
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#define PXA27x_CLKCFG(B, HT, T) \
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(CLKCFG_FCS | \
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((B) ? CLKCFG_FASTBUS : 0) | \
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((HT) ? CLKCFG_HALFTURBO : 0) | \
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((T) ? CLKCFG_TURBO : 0))
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#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
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||||
|
||||
#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
|
||||
#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
|
||||
|
||||
/* Define the refresh period in mSec for the SDRAM and the number of rows */
|
||||
#define SDRAM_TREF 64 /* standard 64ms SDRAM */
|
||||
|
||||
static const char * const get_freq_khz[] = {
|
||||
"core", "run", "cpll", "memory",
|
||||
"system_bus"
|
||||
};
|
||||
|
||||
static int get_sdram_rows(void)
|
||||
{
|
||||
static int sdram_rows;
|
||||
unsigned int drac2 = 0, drac0 = 0;
|
||||
u32 mdcnfg;
|
||||
|
||||
if (sdram_rows)
|
||||
return sdram_rows;
|
||||
|
||||
mdcnfg = readl_relaxed(MDCNFG);
|
||||
|
||||
if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
|
||||
drac2 = MDCNFG_DRAC2(mdcnfg);
|
||||
|
||||
if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
|
||||
drac0 = MDCNFG_DRAC0(mdcnfg);
|
||||
|
||||
sdram_rows = 1 << (11 + max(drac0, drac2));
|
||||
return sdram_rows;
|
||||
}
|
||||
|
||||
static u32 mdrefr_dri(unsigned int freq_khz)
|
||||
{
|
||||
u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
|
||||
|
||||
return (interval - 31) / 32;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the clock frequency as reflected by CCSR and the turbo flag.
|
||||
* We assume these values have been applied via a fcs.
|
||||
|
|
@ -145,6 +188,42 @@ static struct desc_clk_cken pxa27x_clocks[] __initdata = {
|
|||
|
||||
};
|
||||
|
||||
/*
|
||||
* PXA270 definitions
|
||||
*
|
||||
* For the PXA27x:
|
||||
* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
|
||||
*
|
||||
* A = 0 => memory controller clock from table 3-7,
|
||||
* A = 1 => memory controller clock = system bus clock
|
||||
* Run mode frequency = 13 MHz * L
|
||||
* Turbo mode frequency = 13 MHz * L * N
|
||||
* System bus frequency = 13 MHz * L / (B + 1)
|
||||
*
|
||||
* In CCCR:
|
||||
* A = 1
|
||||
* L = 16 oscillator to run mode ratio
|
||||
* 2N = 6 2 * (turbo mode to run mode ratio)
|
||||
*
|
||||
* In CCLKCFG:
|
||||
* B = 1 Fast bus mode
|
||||
* HT = 0 Half-Turbo mode
|
||||
* T = 1 Turbo mode
|
||||
*
|
||||
* For now, just support some of the combinations in table 3-7 of
|
||||
* PXA27x Processor Family Developer's Manual to simplify frequency
|
||||
* change sequences.
|
||||
*/
|
||||
static struct pxa2xx_freq pxa27x_freqs[] = {
|
||||
{104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
|
||||
{156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
|
||||
{208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
|
||||
{312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
|
||||
{416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
|
||||
{520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
|
||||
{624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
|
||||
};
|
||||
|
||||
static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
@ -164,8 +243,33 @@ static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
|
|||
|
||||
return N;
|
||||
}
|
||||
|
||||
static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return pxa2xx_determine_rate(req, pxa27x_freqs,
|
||||
ARRAY_SIZE(pxa27x_freqs));
|
||||
}
|
||||
|
||||
static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
int i;
|
||||
|
||||
pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
|
||||
for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
|
||||
if (pxa27x_freqs[i].cpll == rate)
|
||||
break;
|
||||
|
||||
if (i >= ARRAY_SIZE(pxa27x_freqs))
|
||||
return -EINVAL;
|
||||
|
||||
pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
|
||||
RATE_RO_OPS(clk_pxa27x_cpll, "cpll");
|
||||
RATE_OPS(clk_pxa27x_cpll, "cpll");
|
||||
|
||||
static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
|
|
@ -217,25 +321,6 @@ static void __init pxa27x_register_plls(void)
|
|||
clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
|
||||
}
|
||||
|
||||
static unsigned long clk_pxa27x_core_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long clkcfg;
|
||||
unsigned int ht, osc_forced;
|
||||
unsigned long ccsr = readl(CCSR);
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
|
||||
ht = clkcfg & (1 << 2);
|
||||
|
||||
if (osc_forced)
|
||||
return parent_rate;
|
||||
if (ht)
|
||||
return parent_rate / 2;
|
||||
else
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
unsigned long clkcfg;
|
||||
|
|
@ -254,8 +339,25 @@ static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
|
|||
return PXA_CORE_TURBO;
|
||||
return PXA_CORE_RUN;
|
||||
}
|
||||
|
||||
static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
if (index > PXA_CORE_TURBO)
|
||||
return -EINVAL;
|
||||
|
||||
pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return __clk_mux_determine_rate(hw, req);
|
||||
}
|
||||
|
||||
PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
|
||||
MUX_RO_RATE_RO_OPS(clk_pxa27x_core, "core");
|
||||
MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
|
||||
|
||||
static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
|
|
|
|||
Loading…
Reference in New Issue