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Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/intel config: Fix the APB_TIMER selection
  x86/mrst: Add additional debug prints for pb_keys
  x86/intel config: Revamp configuration to allow for Moorestown and Medfield
  x86/intel/scu/ipc: Match the changes in the x86 configuration
  x86/apb: Fix configuration constraints
  x86: Fix INTEL_MID silly
  x86/Kconfig: Cyclone-timer depends on x86-summit
  x86: Reduce clock calibration time during slave cpu startup
  x86/config: Revamp configuration for MID devices
  x86/sfi: Kill the IRQ as id hack
This commit is contained in:
Linus Torvalds 2012-01-11 19:13:40 -08:00
parent 541048a1d3 7c9c3a1e5f
commit 9fc5c3e323
13 changed files with 89 additions and 25 deletions
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31
arch/x86/Kconfig
View File

@ -420,12 +420,14 @@ config X86_MRST
depends on PCI
depends on PCI_GOANY
depends on X86_IO_APIC
select X86_INTEL_MID
select SFI
select DW_APB_TIMER
select APB_TIMER
select I2C
select SPI
select INTEL_SCU_IPC
select X86_PLATFORM_DEVICES
select X86_INTEL_MID
---help---
Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin
Internet Device(MID) platform. Moorestown consists of two chips:
@ -434,6 +436,26 @@ config X86_MRST
nor standard legacy replacement devices/features. e.g. Moorestown does
not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
config X86_MDFLD
bool "Medfield MID platform"
depends on PCI
depends on PCI_GOANY
depends on X86_IO_APIC
select X86_INTEL_MID
select SFI
select DW_APB_TIMER
select APB_TIMER
select I2C
select SPI
select INTEL_SCU_IPC
select X86_PLATFORM_DEVICES
---help---
Medfield is Intel's Low Power Intel Architecture (LPIA) based Moblin
Internet Device(MID) platform.
Unlike standard x86 PCs, Medfield does not have many legacy devices
nor standard legacy replacement devices/features. e.g. Medfield does
not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
endif
config X86_RDC321X
@ -631,7 +653,7 @@ config X86_SUMMIT_NUMA
config X86_CYCLONE_TIMER
def_bool y
depends on X86_32_NON_STANDARD
depends on X86_SUMMIT
source "arch/x86/Kconfig.cpu"
@ -659,9 +681,10 @@ config HPET_EMULATE_RTC
depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)
config APB_TIMER
def_bool y if MRST
prompt "Langwell APB Timer Support" if X86_MRST
def_bool y if X86_INTEL_MID
prompt "Intel MID APB Timer Support" if X86_INTEL_MID
select DW_APB_TIMER
depends on X86_INTEL_MID && SFI
help
APB timer is the replacement for 8254, HPET on X86 MID platforms.
The APBT provides a stable time base on SMP

6
arch/x86/Kconfig.debug
View File

@ -43,9 +43,9 @@ config EARLY_PRINTK
with klogd/syslogd or the X server. You should normally N here,
unless you want to debug such a crash.
config EARLY_PRINTK_MRST
bool "Early printk for MRST platform support"
depends on EARLY_PRINTK && X86_MRST
config EARLY_PRINTK_INTEL_MID
bool "Early printk for Intel MID platform support"
depends on EARLY_PRINTK && X86_INTEL_MID
config EARLY_PRINTK_DBGP
bool "Early printk via EHCI debug port"

2
arch/x86/include/asm/fixmap.h
View File

@ -117,7 +117,7 @@ enum fixed_addresses {
#endif
FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */
FIX_TEXT_POKE0, /* first page is last, because allocation is backward */
#ifdef CONFIG_X86_MRST
#ifdef CONFIG_X86_INTEL_MID
FIX_LNW_VRTC,
#endif
__end_of_permanent_fixed_addresses,

2
arch/x86/include/asm/setup.h
View File

@ -47,7 +47,7 @@ extern void reserve_standard_io_resources(void);
extern void i386_reserve_resources(void);
extern void setup_default_timer_irq(void);
#ifdef CONFIG_X86_MRST
#ifdef CONFIG_X86_INTEL_MID
extern void x86_mrst_early_setup(void);
#else
static inline void x86_mrst_early_setup(void) { }

2
arch/x86/kernel/early_printk.c
View File

@ -240,7 +240,7 @@ static int __init setup_early_printk(char *buf)
if (!strncmp(buf, "xen", 3))
early_console_register(&xenboot_console, keep);
#endif
#ifdef CONFIG_EARLY_PRINTK_MRST
#ifdef CONFIG_EARLY_PRINTK_INTEL_MID
if (!strncmp(buf, "mrst", 4)) {
mrst_early_console_init();
early_console_register(&early_mrst_console, keep);

16
arch/x86/kernel/smpboot.c
View File

@ -207,22 +207,28 @@ static void __cpuinit smp_callin(void)
* Need to setup vector mappings before we enable interrupts.
*/
setup_vector_irq(smp_processor_id());
/*
* Save our processor parameters. Note: this information
* is needed for clock calibration.
*/
smp_store_cpu_info(cpuid);
/*
* Get our bogomips.
* Update loops_per_jiffy in cpu_data. Previous call to
* smp_store_cpu_info() stored a value that is close but not as
* accurate as the value just calculated.
*
* Need to enable IRQs because it can take longer and then
* the NMI watchdog might kill us.
*/
local_irq_enable();
calibrate_delay();
cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
local_irq_disable();
pr_debug("Stack at about %p\n", &cpuid);
/*
* Save our processor parameters
*/
smp_store_cpu_info(cpuid);
/*
* This must be done before setting cpu_online_mask
* or calling notify_cpu_starting.

20
arch/x86/kernel/tsc.c
View File

@ -995,3 +995,23 @@ void __init tsc_init(void)
check_system_tsc_reliable();
}
#ifdef CONFIG_SMP
/*
* If we have a constant TSC and are using the TSC for the delay loop,
* we can skip clock calibration if another cpu in the same socket has already
* been calibrated. This assumes that CONSTANT_TSC applies to all
* cpus in the socket - this should be a safe assumption.
*/
unsigned long __cpuinit calibrate_delay_is_known(void)
{
int i, cpu = smp_processor_id();
if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
return 0;
for_each_online_cpu(i)
if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
return cpu_data(i).loops_per_jiffy;
return 0;
}
#endif

2
arch/x86/pci/Makefile
View File

@ -15,7 +15,7 @@ obj-$(CONFIG_X86_VISWS) += visws.o
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
obj-$(CONFIG_X86_MRST) += mrst.o
obj-$(CONFIG_X86_INTEL_MID) += mrst.o
obj-y += common.o early.o
obj-y += amd_bus.o bus_numa.o

6
arch/x86/platform/mrst/Makefile
View File

@ -1,4 +1,4 @@
obj-$(CONFIG_X86_MRST) += mrst.o
obj-$(CONFIG_X86_MRST) += vrtc.o
obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o
obj-$(CONFIG_X86_INTEL_MID) += mrst.o
obj-$(CONFIG_X86_INTEL_MID) += vrtc.o
obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_mrst.o
obj-$(CONFIG_X86_MRST) += pmu.o

4
arch/x86/platform/mrst/mrst.c
View File

@ -848,8 +848,7 @@ static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry)
if (mrst_has_msic())
return;
/* ID as IRQ is a hack that will go away */
pdev = platform_device_alloc(entry->name, entry->irq);
pdev = platform_device_alloc(entry->name, 0);
if (pdev == NULL) {
pr_err("out of memory for SFI platform device '%s'.\n",
entry->name);
@ -1030,6 +1029,7 @@ static int __init pb_keys_init(void)
num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
for (i = 0; i < num; i++) {
gb[i].gpio = get_gpio_by_name(gb[i].desc);
pr_debug("info[%2d]: name = %s, gpio = %d\n", i, gb[i].desc, gb[i].gpio);
if (gb[i].gpio == -1)
continue;

2
drivers/platform/x86/Kconfig
View File

@ -639,7 +639,7 @@ config ACPI_CMPC
config INTEL_SCU_IPC
bool "Intel SCU IPC Support"
depends on X86_MRST
depends on X86_INTEL_MID
default y
---help---
IPC is used to bridge the communications between kernel and SCU on

6
drivers/rtc/Kconfig
View File

@ -498,9 +498,9 @@ config RTC_DRV_CMOS
will be called rtc-cmos.
config RTC_DRV_VRTC
tristate "Virtual RTC for Moorestown platforms"
depends on X86_MRST
default y if X86_MRST
tristate "Virtual RTC for Intel MID platforms"
depends on X86_INTEL_MID
default y if X86_INTEL_MID
help
Say "yes" here to get direct support for the real time clock

15
init/calibrate.c
View File

@ -246,6 +246,19 @@ recalibrate:
static DEFINE_PER_CPU(unsigned long, cpu_loops_per_jiffy) = { 0 };
/*
* Check if cpu calibration delay is already known. For example,
* some processors with multi-core sockets may have all cores
* with the same calibration delay.
*
* Architectures should override this function if a faster calibration
* method is available.
*/
unsigned long __attribute__((weak)) __cpuinit calibrate_delay_is_known(void)
{
return 0;
}
void __cpuinit calibrate_delay(void)
{
unsigned long lpj;
@ -265,6 +278,8 @@ void __cpuinit calibrate_delay(void)
lpj = lpj_fine;
pr_info("Calibrating delay loop (skipped), "
"value calculated using timer frequency.. ");
} else if ((lpj = calibrate_delay_is_known())) {
;
} else if ((lpj = calibrate_delay_direct()) != 0) {
if (!printed)
pr_info("Calibrating delay using timer "